Fabiano Fontana

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dual-port SRAM with bit line clamping
- Patent number 8,971,146
- Issue date Mar 3, 2015
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage discharge circuit having divided discharge current
- Patent number 8,553,463
- Issue date Oct 8, 2013
- Lattice Semiconductor Corporation
- Robert Gary Pollachek
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-port SRAM with bit line clamping
- Patent number 8,451,679
- Issue date May 28, 2013
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitline floating circuit for memory power reduction
- Patent number 8,351,287
- Issue date Jan 8, 2013
- Lattice Semiconductor Corporation
- Rohith Sood
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible memory architectures for programmable logic devices
- Patent number 7,957,208
- Issue date Jun 7, 2011
- Lattice Semiconductor Corporation
- Howard Tang
- G11 - INFORMATION STORAGE
Information Patent Grant
Power management for integrated circuits such as programmable logic...
- Patent number 7,724,029
- Issue date May 25, 2010
- Lattice Semiconductor Corporation
- Satwant Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with custom identification systems and m...
- Patent number 7,702,977
- Issue date Apr 20, 2010
- Lattice Semiconductor Corporation
- Howard Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management systems and methods for programmable logic devices
- Patent number 7,560,953
- Issue date Jul 14, 2009
- Lattice Semiconductor Corporation
- Satwant Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with user non-volatile memory
- Patent number 7,554,358
- Issue date Jun 30, 2009
- Lattice Semiconductor Corporation
- Fabiano Fontana
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with custom identification systems and m...
- Patent number 7,546,498
- Issue date Jun 9, 2009
- Lattice Semiconductor Corporation
- Howard Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible memory architectures for programmable logic devices
- Patent number 7,495,970
- Issue date Feb 24, 2009
- Lattice Semiconductor Corporation
- Howard Tang
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic devices with transparent field reconfiguration
- Patent number 7,459,931
- Issue date Dec 2, 2008
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device providing a serial peripheral interface
- Patent number 7,378,873
- Issue date May 27, 2008
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Zero-power programmable memory cell
- Patent number RE40311
- Issue date May 13, 2008
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- 365 - Static information storage and retrieval
Information Patent Grant
Flash memory erase verification systems and methods
- Patent number 7,313,025
- Issue date Dec 25, 2007
- Lattice Semiconductor Corporation
- Hok Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory erase verification systems and methods
- Patent number 7,187,586
- Issue date Mar 6, 2007
- Lattice Semiconductor Corporation
- Hok Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced CPLD macrocell module having selectable bypass of steering...
- Patent number 6,838,904
- Issue date Jan 4, 2005
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Enhanced CPLD macrocell module having selectable bypass of steering...
- Patent number 6,650,142
- Issue date Nov 18, 2003
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Zero-power programmable memory cell
- Patent number 6,611,463
- Issue date Aug 26, 2003
- Lattice Semiconductor Corporation
- Sunil Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero-power logic cell for use in programmable logic devices
- Patent number 6,489,806
- Issue date Dec 3, 2002
- Lattice Semiconductor Corporation
- Sunil Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase locked loop with a lock detector
- Patent number 6,133,769
- Issue date Oct 17, 2000
- Vantis Corporation
- Fabiano Fontana
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Enhanced method of testing semiconductor devices having nonvolatile...
- Patent number 5,982,683
- Issue date Nov 9, 1999
- Advanced Micro Devices, Inc.
- James A. Watson
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DUAL-PORT SRAM WITH BIT LINE CLAMPING
- Publication number 20130258761
- Publication date Oct 3, 2013
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G11 - INFORMATION STORAGE
Information Patent Application
Variable source resistor for flash memory
- Publication number 20070030736
- Publication date Feb 8, 2007
- Fabiano Fontana
- G11 - INFORMATION STORAGE
Information Patent Application
Diode structure for word-line protection in a memory circuit
- Publication number 20060145238
- Publication date Jul 6, 2006
- Fabiano Fontana
- G11 - INFORMATION STORAGE

Fabiano Fontana

Person

Patents Grantslast 30 patents

Dual-port SRAM with bit line clamping

Voltage discharge circuit having divided discharge current

Dual-port SRAM with bit line clamping

Bitline floating circuit for memory power reduction

Flexible memory architectures for programmable logic devices

Power management for integrated circuits such as programmable logic...

Programmable logic devices with custom identification systems and m...

Power management systems and methods for programmable logic devices

Programmable logic devices with user non-volatile memory

Programmable logic devices with custom identification systems and m...

Flexible memory architectures for programmable logic devices

Programmable logic devices with transparent field reconfiguration

Programmable logic device providing a serial peripheral interface

Zero-power programmable memory cell

Flash memory erase verification systems and methods

Flash memory erase verification systems and methods

Enhanced CPLD macrocell module having selectable bypass of steering...

Enhanced CPLD macrocell module having selectable bypass of steering...

Zero-power programmable memory cell

Zero-power logic cell for use in programmable logic devices

Phase locked loop with a lock detector

Enhanced method of testing semiconductor devices having nonvolatile...

Patents Applicationslast 30 patents

DUAL-PORT SRAM WITH BIT LINE CLAMPING

Variable source resistor for flash memory

Diode structure for word-line protection in a memory circuit