Fabio Checconi

Person

Santa Clara, CA, US

People

Patents Applicationslast 30 patents

Information Patent Application
INSTRUCTION SET ARCHITECTURE AND HARDWARE SUPPORT FOR HASH OPERATIONS
- Publication number 20240241645
- Publication date Jul 18, 2024
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY RECONFIGURABLE PROCESSING CORE
- Publication number 20240069921
- Publication date Feb 29, 2024
- Intel Corporation
- Scott Cline
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION SET ARCHITECTURE SUPPORT FOR DATA TYPE CONVERSION IN NE...
- Publication number 20240020253
- Publication date Jan 18, 2024
- Intel Corporation
- Shruti Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION SET ARCHITECTURE SUPPORT FOR CONDITIONAL DIRECT MEMORY...
- Publication number 20230333998
- Publication date Oct 19, 2023
- Intel Corporation
- Shruti Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO ACCELERATE MATRIX OPERATIONS USING DIRECT...
- Publication number 20230325185
- Publication date Oct 12, 2023
- Intel Corporation
- Jesmin Jahan Tithi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGY TO SUPPORT BITMAP MANIPULATION OPERATIONS USING A DIRECT...
- Publication number 20230315451
- Publication date Oct 5, 2023
- Intel Corporation
- Shruti Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETURN VALUE STORAGE FOR ATOMIC FUNCTIONS
- Publication number 20230095207
- Publication date Mar 30, 2023
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING

Fabio Checconi

Person

Patents Applicationslast 30 patents

INSTRUCTION SET ARCHITECTURE AND HARDWARE SUPPORT FOR HASH OPERATIONS

DYNAMICALLY RECONFIGURABLE PROCESSING CORE

INSTRUCTION SET ARCHITECTURE SUPPORT FOR DATA TYPE CONVERSION IN NE...

INSTRUCTION SET ARCHITECTURE SUPPORT FOR CONDITIONAL DIRECT MEMORY...

METHODS AND APPARATUS TO ACCELERATE MATRIX OPERATIONS USING DIRECT...

TECHNOLOGY TO SUPPORT BITMAP MANIPULATION OPERATIONS USING A DIRECT...

RETURN VALUE STORAGE FOR ATOMIC FUNCTIONS