Fabio Pellizzer

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Unipolar programming of memory cells
- Patent number 12,367,933
- Issue date Jul 22, 2025
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Vertical memory architecture
- Patent number 12,349,371
- Issue date Jul 1, 2025
- Micron Technology, Inc.
- Agostino Pirovano
Information Patent Grant
Devices including a passive material between memory cells and condu...
- Patent number 12,336,193
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Innocenzo Tortorelli
Information Patent Grant
Cross-point pillar architecture for memory arrays
- Patent number 12,283,316
- Issue date Apr 22, 2025
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoder architectures for three-dimensional memory devices
- Patent number 12,236,999
- Issue date Feb 25, 2025
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Folded access line for memory cell access in a memory device
- Patent number 12,219,782
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Srivatsan Venkatesan
Information Patent Grant
Techniques for forming self-aligned memory structures
- Patent number 12,219,883
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Stephen W. Russell
Information Patent Grant
Memory device and method for manufacturing the same
- Patent number 12,219,784
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Lorenzo Fratin
Information Patent Grant
Split pillar architectures for memory devices
- Patent number 12,178,054
- Issue date Dec 24, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Grant
Operating a chalcogenide memory with vertical word and vertical wor...
- Patent number 12,176,042
- Issue date Dec 24, 2024
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with a split pillar architecture
- Patent number 12,171,105
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method for manufacturing the same
- Patent number 12,150,317
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
Information Patent Grant
Decoding for a memory device
- Patent number 12,148,467
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-selecting memory array with horizontal access lines
- Patent number 12,100,447
- Issue date Sep 24, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Identify the programming mode of memory cells during reading of the...
- Patent number 12,080,359
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cells with asymmetrical electrode interfaces
- Patent number 12,082,513
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked artificial neural networks
- Patent number 12,026,601
- Issue date Jul 2, 2024
- Micron Technology, Inc.
- Fabio Pellizzer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reading a multi-level memory cell
- Patent number 11,996,141
- Issue date May 28, 2024
- Micron Technology, Inc.
- Mattia Robustelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Varying-polarity read operations for polarity-written memory cells
- Patent number 11,923,002
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Dirty write on power off
- Patent number 11,923,007
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding architecture for word line tiles
- Patent number 11,894,103
- Issue date Feb 6, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross-point pillar architecture for memory arrays
- Patent number 11,887,661
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding architecture for memory devices
- Patent number 11,869,577
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for pre-read scan of memory devices
- Patent number 11,862,226
- Issue date Jan 2, 2024
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel drift cancellation
- Patent number 11,848,051
- Issue date Dec 19, 2023
- Micron Technology, Inc.
- Fabio Pellizzer
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for programming a memory cell
- Patent number 11,817,148
- Issue date Nov 14, 2023
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses including multi-level memory cells and methods of opera...
- Patent number 11,798,620
- Issue date Oct 24, 2023
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding for a memory device
- Patent number 11,790,987
- Issue date Oct 17, 2023
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level self-selecting memory device
- Patent number 11,769,551
- Issue date Sep 26, 2023
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Microelectronic devices with self-aligned interconnects, and relate...
- Patent number 11,764,146
- Issue date Sep 19, 2023
- Micron Technology, Inc.
- Stephen W. Russell
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY DEVICES
- Publication number 20250232799
- Publication date Jul 17, 2025
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20250234560
- Publication date Jul 17, 2025
- Micron Technology, Inc.
- Lorenzo Fratin
Information Patent Application
CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS
- Publication number 20250226029
- Publication date Jul 10, 2025
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
OPERATING A CHALCOGENIDE MEMORY WITH VERTICAL WORD AND VERTICAL WOR...
- Publication number 20250174283
- Publication date May 29, 2025
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH A SPLIT PILLAR ARCHITECTURE
- Publication number 20250159910
- Publication date May 15, 2025
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
FOLDED ACCESS LINE FOR MEMORY CELL ACCESS IN A MEMORY DEVICE
- Publication number 20250142838
- Publication date May 1, 2025
- Micron Technology, Inc.
- Srivatsan Venkatesan
Information Patent Application
MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20250120098
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Lorenzo Fratin
Information Patent Application
SPLIT PILLAR ARCHITECTURES FOR MEMORY DEVICES
- Publication number 20250107105
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES
- Publication number 20250061943
- Publication date Feb 20, 2025
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
DECODING FOR A MEMORY DEVICE
- Publication number 20250037761
- Publication date Jan 30, 2025
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Application
IDENTIFY THE PROGRAMMING MODE OF MEMORY CELLS DURING READING OF THE...
- Publication number 20240404606
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Application
READING A MULTI-LEVEL MEMORY CELL
- Publication number 20240321347
- Publication date Sep 26, 2024
- Micron Technology, Inc.
- Mattia Robustelli
- G11 - INFORMATION STORAGE
Information Patent Application
VARYING-POLARITY READ OPERATIONS FOR POLARITY-WRITTEN MEMORY CELLS
- Publication number 20240312518
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
TRENCH AND MULTIPLE PIER ARCHITECTURE FOR THREE-DIMENSIONAL MEMORY...
- Publication number 20240312521
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Fabio Pellizzer
- G11 - INFORMATION STORAGE
Information Patent Application
SPLIT PILLAR AND PIER MEMORY ARCHITECTURES
- Publication number 20240284660
- Publication date Aug 22, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
LATERAL SPLIT DIGIT LINE MEMORY ARCHITECTURES
- Publication number 20240284659
- Publication date Aug 22, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
USING A SUBTHRESHOLD VOLTAGE FOR MAPPING IN MEMORY
- Publication number 20240242771
- Publication date Jul 18, 2024
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS
- Publication number 20240221829
- Publication date Jul 4, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
DECODING ARCHITECTURE FOR MEMORY DEVICES
- Publication number 20240203481
- Publication date Jun 20, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Application
DECODING ARCHITECTURE FOR WORD LINE TILES
- Publication number 20240161801
- Publication date May 16, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY AND STORAGE ON A SINGLE CHIP
- Publication number 20240130143
- Publication date Apr 18, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES...
- Publication number 20240074168
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Paolo Fantini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIPOLAR PROGRAMMING OF MEMORY CELLS
- Publication number 20240029796
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY DEVICES
- Publication number 20230395128
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
TRENCH AND PIER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
- Publication number 20230329010
- Publication date Oct 12, 2023
- Micron Technology, Inc.
- Fabio Pellizzer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Adaptively Programming Memory Cells in Different Modes to Optimize...
- Publication number 20230268005
- Publication date Aug 24, 2023
- Micron Technology, Inc.
- Karthik Sarpatwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR OPERATING A VERTICAL MEMORY ARCHITECTURE
- Publication number 20230260581
- Publication date Aug 17, 2023
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
VERTICAL MEMORY ARCHITECTURE
- Publication number 20230262995
- Publication date Aug 17, 2023
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DECODING ARCHITECTURE FOR MEMORY DEVICES
- Publication number 20230238050
- Publication date Jul 27, 2023
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Application
IDENTIFY THE PROGRAMMING MODE OF MEMORY CELLS DURING READING OF THE...
- Publication number 20230230642
- Publication date Jul 20, 2023
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE

Fabio Pellizzer

Person

Patents Grantslast 30 patents

Unipolar programming of memory cells

Vertical memory architecture

Devices including a passive material between memory cells and condu...

Cross-point pillar architecture for memory arrays

Decoder architectures for three-dimensional memory devices

Folded access line for memory cell access in a memory device

Techniques for forming self-aligned memory structures

Memory device and method for manufacturing the same

Split pillar architectures for memory devices

Operating a chalcogenide memory with vertical word and vertical wor...

Memory device with a split pillar architecture

Memory device and method for manufacturing the same

Decoding for a memory device

Self-selecting memory array with horizontal access lines

Identify the programming mode of memory cells during reading of the...

Memory cells with asymmetrical electrode interfaces

Stacked artificial neural networks

Reading a multi-level memory cell

Varying-polarity read operations for polarity-written memory cells

Dirty write on power off

Decoding architecture for word line tiles

Cross-point pillar architecture for memory arrays

Decoding architecture for memory devices

Systems and methods for pre-read scan of memory devices

Parallel drift cancellation

Techniques for programming a memory cell

Apparatuses including multi-level memory cells and methods of opera...

Decoding for a memory device

Multi-level self-selecting memory device

Microelectronic devices with self-aligned interconnects, and relate...

Patents Applicationslast 30 patents

DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY DEVICES

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS

OPERATING A CHALCOGENIDE MEMORY WITH VERTICAL WORD AND VERTICAL WOR...

MEMORY DEVICE WITH A SPLIT PILLAR ARCHITECTURE

FOLDED ACCESS LINE FOR MEMORY CELL ACCESS IN A MEMORY DEVICE

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

SPLIT PILLAR ARCHITECTURES FOR MEMORY DEVICES

SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES

DECODING FOR A MEMORY DEVICE

IDENTIFY THE PROGRAMMING MODE OF MEMORY CELLS DURING READING OF THE...

READING A MULTI-LEVEL MEMORY CELL

VARYING-POLARITY READ OPERATIONS FOR POLARITY-WRITTEN MEMORY CELLS

TRENCH AND MULTIPLE PIER ARCHITECTURE FOR THREE-DIMENSIONAL MEMORY...

SPLIT PILLAR AND PIER MEMORY ARCHITECTURES

LATERAL SPLIT DIGIT LINE MEMORY ARCHITECTURES

USING A SUBTHRESHOLD VOLTAGE FOR MAPPING IN MEMORY

CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS

DECODING ARCHITECTURE FOR MEMORY DEVICES

DECODING ARCHITECTURE FOR WORD LINE TILES

MEMORY AND STORAGE ON A SINGLE CHIP

MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES...

UNIPOLAR PROGRAMMING OF MEMORY CELLS

DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY DEVICES

TRENCH AND PIER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS

Adaptively Programming Memory Cells in Different Modes to Optimize...

TECHNIQUES FOR OPERATING A VERTICAL MEMORY ARCHITECTURE

VERTICAL MEMORY ARCHITECTURE

DECODING ARCHITECTURE FOR MEMORY DEVICES

IDENTIFY THE PROGRAMMING MODE OF MEMORY CELLS DURING READING OF THE...