Fabio Pellizzer

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory device with a split pillar architecture
- Patent number 12,171,105
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method for manufacturing the same
- Patent number 12,150,317
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
Information Patent Grant
Decoding for a memory device
- Patent number 12,148,467
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-selecting memory array with horizontal access lines
- Patent number 12,100,447
- Issue date Sep 24, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Identify the programming mode of memory cells during reading of the...
- Patent number 12,080,359
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cells with asymmetrical electrode interfaces
- Patent number 12,082,513
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked artificial neural networks
- Patent number 12,026,601
- Issue date Jul 2, 2024
- Micron Technology, Inc.
- Fabio Pellizzer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reading a multi-level memory cell
- Patent number 11,996,141
- Issue date May 28, 2024
- Micron Technology, Inc.
- Mattia Robustelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Varying-polarity read operations for polarity-written memory cells
- Patent number 11,923,002
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Dirty write on power off
- Patent number 11,923,007
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding architecture for word line tiles
- Patent number 11,894,103
- Issue date Feb 6, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross-point pillar architecture for memory arrays
- Patent number 11,887,661
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding architecture for memory devices
- Patent number 11,869,577
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for pre-read scan of memory devices
- Patent number 11,862,226
- Issue date Jan 2, 2024
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel drift cancellation
- Patent number 11,848,051
- Issue date Dec 19, 2023
- Micron Technology, Inc.
- Fabio Pellizzer
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for programming a memory cell
- Patent number 11,817,148
- Issue date Nov 14, 2023
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses including multi-level memory cells and methods of opera...
- Patent number 11,798,620
- Issue date Oct 24, 2023
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding for a memory device
- Patent number 11,790,987
- Issue date Oct 17, 2023
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level self-selecting memory device
- Patent number 11,769,551
- Issue date Sep 26, 2023
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Microelectronic devices with self-aligned interconnects, and relate...
- Patent number 11,764,146
- Issue date Sep 19, 2023
- Micron Technology, Inc.
- Stephen W. Russell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional memory arrays
- Patent number 11,765,912
- Issue date Sep 19, 2023
- Micron Technology, Inc.
- Agostino Pirovano
Information Patent Grant
Techniques to access a self-selecting memory device
- Patent number 11,763,886
- Issue date Sep 19, 2023
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming enhancement in self-selecting memory
- Patent number 11,735,261
- Issue date Aug 22, 2023
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Capacitive pillar architecture for a memory array
- Patent number 11,729,999
- Issue date Aug 15, 2023
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Polarity-written cell architectures for a memory device
- Patent number 11,721,394
- Issue date Aug 8, 2023
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Three dimensional memory arrays
- Patent number 11,696,454
- Issue date Jul 4, 2023
- Micron Technology, Inc.
- Fabio Pellizzer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory operation with double-sided asymmetric decoders
- Patent number 11,688,460
- Issue date Jun 27, 2023
- Micron Technology, Inc.
- Fabio Pellizzer
- G11 - INFORMATION STORAGE
Information Patent Grant
Two memory cells sensed to determine one data value
- Patent number 11,670,367
- Issue date Jun 6, 2023
- Micron Technology, Inc.
- Fabio Pellizzer
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptively programming memory cells in different modes to optimize...
- Patent number 11,664,073
- Issue date May 30, 2023
- Micron Technology, Inc.
- Karthik Sarpatwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with double protective liner
- Patent number 11,647,638
- Issue date May 9, 2023
- Intel Corporation
- Anna Maria Conti
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
IDENTIFY THE PROGRAMMING MODE OF MEMORY CELLS DURING READING OF THE...
- Publication number 20240404606
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Application
READING A MULTI-LEVEL MEMORY CELL
- Publication number 20240321347
- Publication date Sep 26, 2024
- Micron Technology, Inc.
- Mattia Robustelli
- G11 - INFORMATION STORAGE
Information Patent Application
VARYING-POLARITY READ OPERATIONS FOR POLARITY-WRITTEN MEMORY CELLS
- Publication number 20240312518
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
TRENCH AND MULTIPLE PIER ARCHITECTURE FOR THREE-DIMENSIONAL MEMORY...
- Publication number 20240312521
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Fabio Pellizzer
- G11 - INFORMATION STORAGE
Information Patent Application
SPLIT PILLAR AND PIER MEMORY ARCHITECTURES
- Publication number 20240284660
- Publication date Aug 22, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
LATERAL SPLIT DIGIT LINE MEMORY ARCHITECTURES
- Publication number 20240284659
- Publication date Aug 22, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
USING A SUBTHRESHOLD VOLTAGE FOR MAPPING IN MEMORY
- Publication number 20240242771
- Publication date Jul 18, 2024
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS
- Publication number 20240221829
- Publication date Jul 4, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
DECODING ARCHITECTURE FOR MEMORY DEVICES
- Publication number 20240203481
- Publication date Jun 20, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Application
DECODING ARCHITECTURE FOR WORD LINE TILES
- Publication number 20240161801
- Publication date May 16, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY AND STORAGE ON A SINGLE CHIP
- Publication number 20240130143
- Publication date Apr 18, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES...
- Publication number 20240074168
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Paolo Fantini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIPOLAR PROGRAMMING OF MEMORY CELLS
- Publication number 20240029796
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY DEVICES
- Publication number 20230395128
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
TRENCH AND PIER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
- Publication number 20230329010
- Publication date Oct 12, 2023
- Micron Technology, Inc.
- Fabio Pellizzer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Adaptively Programming Memory Cells in Different Modes to Optimize...
- Publication number 20230268005
- Publication date Aug 24, 2023
- Micron Technology, Inc.
- Karthik Sarpatwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR OPERATING A VERTICAL MEMORY ARCHITECTURE
- Publication number 20230260581
- Publication date Aug 17, 2023
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
VERTICAL MEMORY ARCHITECTURE
- Publication number 20230262995
- Publication date Aug 17, 2023
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DECODING ARCHITECTURE FOR MEMORY DEVICES
- Publication number 20230238050
- Publication date Jul 27, 2023
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Application
IDENTIFY THE PROGRAMMING MODE OF MEMORY CELLS DURING READING OF THE...
- Publication number 20230230642
- Publication date Jul 20, 2023
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS
- Publication number 20230207002
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
FOLDED ACCESS LINE FOR MEMORY CELL ACCESS IN A MEMORY DEVICE
- Publication number 20230171968
- Publication date Jun 1, 2023
- Micron Technology, Inc.
- Srivatsan Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PARALLEL DRIFT CANCELLATION
- Publication number 20230081492
- Publication date Mar 16, 2023
- Micron Technology, Inc.
- Fabio Pellizzer
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR PRE-READ SCAN OF MEMORY DEVICES
- Publication number 20230067396
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Application
DIRTY WRITE ON POWER OFF
- Publication number 20230060231
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Application
Identify the Programming Mode of Memory Cells based on Cell Statist...
- Publication number 20230058300
- Publication date Feb 23, 2023
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Application
DECODING FOR A MEMORY DEVICE
- Publication number 20230032006
- Publication date Feb 2, 2023
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICES INCLUDING A PASSIVE MATERIAL BETWEEN MEMORY CELLS AND CONDU...
- Publication number 20230029529
- Publication date Feb 2, 2023
- Micron Technology, Inc.
- Innocenzo Tortorelli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES
- Publication number 20230027799
- Publication date Jan 26, 2023
- Micron Technology, Inc.
- Stephen W. Russell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES
- Publication number 20230005535
- Publication date Jan 5, 2023
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE

Fabio Pellizzer

Person

Patents Grantslast 30 patents

Memory device with a split pillar architecture

Memory device and method for manufacturing the same

Decoding for a memory device

Self-selecting memory array with horizontal access lines

Identify the programming mode of memory cells during reading of the...

Memory cells with asymmetrical electrode interfaces

Stacked artificial neural networks

Reading a multi-level memory cell

Varying-polarity read operations for polarity-written memory cells

Dirty write on power off

Decoding architecture for word line tiles

Cross-point pillar architecture for memory arrays

Decoding architecture for memory devices

Systems and methods for pre-read scan of memory devices

Parallel drift cancellation

Techniques for programming a memory cell

Apparatuses including multi-level memory cells and methods of opera...

Decoding for a memory device

Multi-level self-selecting memory device

Microelectronic devices with self-aligned interconnects, and relate...

Three dimensional memory arrays

Techniques to access a self-selecting memory device

Programming enhancement in self-selecting memory

Capacitive pillar architecture for a memory array

Polarity-written cell architectures for a memory device

Three dimensional memory arrays

Memory operation with double-sided asymmetric decoders

Two memory cells sensed to determine one data value

Adaptively programming memory cells in different modes to optimize...

Memory device with double protective liner

Patents Applicationslast 30 patents

IDENTIFY THE PROGRAMMING MODE OF MEMORY CELLS DURING READING OF THE...

READING A MULTI-LEVEL MEMORY CELL

VARYING-POLARITY READ OPERATIONS FOR POLARITY-WRITTEN MEMORY CELLS

TRENCH AND MULTIPLE PIER ARCHITECTURE FOR THREE-DIMENSIONAL MEMORY...

SPLIT PILLAR AND PIER MEMORY ARCHITECTURES

LATERAL SPLIT DIGIT LINE MEMORY ARCHITECTURES

USING A SUBTHRESHOLD VOLTAGE FOR MAPPING IN MEMORY

CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS

DECODING ARCHITECTURE FOR MEMORY DEVICES

DECODING ARCHITECTURE FOR WORD LINE TILES

MEMORY AND STORAGE ON A SINGLE CHIP

MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES...

UNIPOLAR PROGRAMMING OF MEMORY CELLS

DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY DEVICES

TRENCH AND PIER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS

Adaptively Programming Memory Cells in Different Modes to Optimize...

TECHNIQUES FOR OPERATING A VERTICAL MEMORY ARCHITECTURE

VERTICAL MEMORY ARCHITECTURE

DECODING ARCHITECTURE FOR MEMORY DEVICES

IDENTIFY THE PROGRAMMING MODE OF MEMORY CELLS DURING READING OF THE...

CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS

FOLDED ACCESS LINE FOR MEMORY CELL ACCESS IN A MEMORY DEVICE

PARALLEL DRIFT CANCELLATION

SYSTEMS AND METHODS FOR PRE-READ SCAN OF MEMORY DEVICES

DIRTY WRITE ON POWER OFF

Identify the Programming Mode of Memory Cells based on Cell Statist...

DECODING FOR A MEMORY DEVICE

DEVICES INCLUDING A PASSIVE MATERIAL BETWEEN MEMORY CELLS AND CONDU...

TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES

SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES