Fadi Maamari

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Automated determinaton of failure mode distribution
- Patent number 11,842,134
- Issue date Dec 12, 2023
- Synopsys, Inc.
- Fadi Maamari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine-learning-based design-for-test (DFT) recommendation system...
- Patent number 11,829,692
- Issue date Nov 28, 2023
- Synopsys, Inc.
- Apik A Zorian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design modification for localization of scan cha...
- Patent number 11,288,428
- Issue date Mar 29, 2022
- Synopsys, Inc.
- Emil I. Gizdarski
- G01 - MEASURING TESTING
Information Patent Grant
Computer system for generating an integrated and unified view of IP...
- Patent number 8,788,993
- Issue date Jul 22, 2014
- Atrenta, Inc.
- Sridhar Gangadharan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating an integrated and unified view of IP-cores fo...
- Patent number 8,533,647
- Issue date Sep 10, 2013
- Atrenta, Inc.
- Sridhar Gangadharan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clocking methodology for at-speed testing of scan circuits with syn...
- Patent number 7,424,656
- Issue date Sep 9, 2008
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method of and program product for performing gate-level diagnosis o...
- Patent number 7,191,374
- Issue date Mar 13, 2007
- LogicVision, Inc.
- Fadi Maamari
- G01 - MEASURING TESTING
Information Patent Grant
Method and program product for detecting bus conflict and floating...
- Patent number 6,883,134
- Issue date Apr 19, 2005
- LogicVision, Inc.
- Fadi Maamari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing high performance circuits
- Patent number 6,510,534
- Issue date Jan 21, 2003
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and program product for modeling circuits with latch based d...
- Patent number 6,457,161
- Issue date Sep 24, 2002
- Benoit Nadeau-Dostie
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AUTOMATED DETERMINATON OF FAILURE MODE DISTRIBUTION
- Publication number 20220100937
- Publication date Mar 31, 2022
- Synopsys, Inc.
- Fadi MAAMARI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER SYSTEM FOR GENERATING AN INTEGRATED AND UNIFIED VIEW OF IP...
- Publication number 20140101630
- Publication date Apr 10, 2014
- ATRENTA, INC.
- Sridhar Gangadharan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Insertion of embedded test in RTL to GDSII flow
- Publication number 20050273683
- Publication date Dec 8, 2005
- LogicVision, Inc.
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
Clocking methodology for at-speed testing of scan circuits with syn...
- Publication number 20050240790
- Publication date Oct 27, 2005
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Method of and program product for performing gate-level diagnosis o...
- Publication number 20030217315
- Publication date Nov 20, 2003
- Fadi Maamari
- G01 - MEASURING TESTING
Information Patent Application
Method and program product for detecting bus conflict and floating...
- Publication number 20020144211
- Publication date Oct 3, 2002
- Fadi Maamari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND PROGRAM PRODUCT FOR MODELING CIRCUITS WITH LATCH BASED D...
- Publication number 20020143515
- Publication date Oct 3, 2002
- Benoit Nadeau-Dostie
- G06 - COMPUTING CALCULATING COUNTING

Fadi Maamari

Person

Patents Grantslast 30 patents

Automated determinaton of failure mode distribution

Machine-learning-based design-for-test (DFT) recommendation system...

Integrated circuit design modification for localization of scan cha...

Computer system for generating an integrated and unified view of IP...

Method for generating an integrated and unified view of IP-cores fo...

Clocking methodology for at-speed testing of scan circuits with syn...

Method of and program product for performing gate-level diagnosis o...

Method and program product for detecting bus conflict and floating...

Method and apparatus for testing high performance circuits

Method and program product for modeling circuits with latch based d...

Patents Applicationslast 30 patents

AUTOMATED DETERMINATON OF FAILURE MODE DISTRIBUTION

COMPUTER SYSTEM FOR GENERATING AN INTEGRATED AND UNIFIED VIEW OF IP...

Insertion of embedded test in RTL to GDSII flow

Clocking methodology for at-speed testing of scan circuits with syn...

Method of and program product for performing gate-level diagnosis o...

Method and program product for detecting bus conflict and floating...

METHOD AND PROGRAM PRODUCT FOR MODELING CIRCUITS WITH LATCH BASED D...