Fangwen Fu

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Supporting 8-bit floating point format operands in a computing arch...
- Patent number 12,242,846
- Issue date Mar 4, 2025
- Intel Corporation
- Naveen Mellempudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for block sparse operations on a systolic array
- Patent number 12,198,222
- Issue date Jan 14, 2025
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual pipeline parallel systolic array
- Patent number 12,189,571
- Issue date Jan 7, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Matrix operation optimization mechanism
- Patent number 12,039,000
- Issue date Jul 16, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical thread scheduling based on multiple barriers
- Patent number 11,977,895
- Issue date May 7, 2024
- Intel Corporation
- Sabareesh Ganapathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dot product operations on sparse matrix elements
- Patent number 11,842,423
- Issue date Dec 12, 2023
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lossless pixel compression based on inferred control information
- Patent number 11,729,403
- Issue date Aug 15, 2023
- Intel Corporation
- James Holland
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Matrix operation optimization mechanism
- Patent number 11,593,454
- Issue date Feb 28, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-based and target-based graphics quality adjustment
- Patent number 11,423,507
- Issue date Aug 23, 2022
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MV/mode prediction, ROI-based transmit, metadata capture, and forma...
- Patent number 11,051,038
- Issue date Jun 29, 2021
- Intel Corporation
- Jill M. Boyce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective coding
- Patent number 10,924,744
- Issue date Feb 16, 2021
- Intel Corporation
- Fangwen Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-based and target-based graphics quality adjustment
- Patent number 10,909,653
- Issue date Feb 2, 2021
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed reality coding with overlays
- Patent number 10,872,441
- Issue date Dec 22, 2020
- Intel Corporation
- Jill M. Boyce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Temporal motion vector prediction control in video coding
- Patent number 10,848,779
- Issue date Nov 24, 2020
- Intel Corporation
- Fangwen Fu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for hardware video encoding
- Patent number 10,715,818
- Issue date Jul 14, 2020
- Intel Corporation
- James M. Holland
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Coding tools for subjective quality improvements in video codecs
- Patent number 10,587,875
- Issue date Mar 10, 2020
- Intel Corporation
- Fangwen Fu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system of high throughput arithmetic entropy coding for...
- Patent number 10,554,977
- Issue date Feb 4, 2020
- Intel Corporation
- Fangwen Fu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Block level rate distortion optimized quantization
- Patent number 10,547,839
- Issue date Jan 28, 2020
- Intel Corporation
- Fangwen Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Temporal motion vector prediction control in video coding
- Patent number 10,542,279
- Issue date Jan 21, 2020
- Intel Corporation
- Fangwen Fu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
MV/mode prediction, ROI-based transmit, metadata capture, and forma...
- Patent number 10,506,255
- Issue date Dec 10, 2019
- Intel Corporation
- Jill M. Boyce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed reality coding with overlays
- Patent number 10,424,082
- Issue date Sep 24, 2019
- Intel Corporation
- Jill M. Boyce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-based and target-based graphics quality adjustment
- Patent number 10,402,932
- Issue date Sep 3, 2019
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for hardware video encoding
- Patent number 10,291,925
- Issue date May 14, 2019
- Intel Corporation
- James M. Holland
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system of entropy coding using look-up table based proba...
- Patent number 10,097,833
- Issue date Oct 9, 2018
- Intel Corporation
- Fangwen Fu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Motion estimation methods for residual prediction
- Patent number 9,386,311
- Issue date Jul 5, 2016
- Intel Corporation
- Sang-Hee Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE REGISTER ALLOCATION SIZES FOR GPU HARDWARE THREADS
- Publication number 20250147762
- Publication date May 8, 2025
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL PIPELINE PARALLEL SYSTOLIC ARRAY
- Publication number 20250117359
- Publication date Apr 10, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERSION OPERATIONS AND SPECIAL VALUE USE CASES SUPPORTING 8-BIT...
- Publication number 20250110733
- Publication date Apr 3, 2025
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING 8-BIT FLOATING POINT FORMAT FOR PARALLEL COMPUTING AND S...
- Publication number 20250110741
- Publication date Apr 3, 2025
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Publication number 20250104180
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER T...
- Publication number 20250068423
- Publication date Feb 27, 2025
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLI...
- Publication number 20250037347
- Publication date Jan 30, 2025
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOATING-POINT CONVERSION VIA AN INTEGER UNIT
- Publication number 20250036361
- Publication date Jan 30, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...
- Publication number 20250036412
- Publication date Jan 30, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MATRIX OPERATION OPTIMIZATION MECHANISM
- Publication number 20240427842
- Publication date Dec 26, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...
- Publication number 20240256274
- Publication date Aug 1, 2024
- Intel Corporation
- Naveen Mellempudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NAMED AND CLUSTER BARRIERS
- Publication number 20240231957
- Publication date Jul 11, 2024
- Intel Corporation
- Fangwen Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BROADCAST ASYNCHRONOUS LOADS TO SHARED LOCAL MEMORY
- Publication number 20240232088
- Publication date Jul 11, 2024
- Intel Corporation
- John A. Wiegert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONIZATION FOR DATA MULTICAST IN COMPUTE CORE CLUSTERS
- Publication number 20240220335
- Publication date Jul 4, 2024
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE AND CONFIGURABLE CLUSTERED SYSTOLIC ARRAY
- Publication number 20240220448
- Publication date Jul 4, 2024
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA MULTICAST IN COMPUTE CORE CLUSTERS
- Publication number 20240220254
- Publication date Jul 4, 2024
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS-THREAD REGISTER SHARING FOR MATRIX MULTIPLICATION COMPUTE
- Publication number 20240168807
- Publication date May 23, 2024
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCEMENTS FOR ACCUMULATOR USAGE AND INSTRUCTION FORWARDING IN MA...
- Publication number 20240169021
- Publication date May 23, 2024
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Publication number 20240161227
- Publication date May 16, 2024
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NAMED AND CLUSTER BARRIERS
- Publication number 20240134719
- Publication date Apr 25, 2024
- Intel Corporation
- Fangwen Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BROADCAST ASYNCHRONOUS LOADS TO SHARED LOCAL MEMORY
- Publication number 20240134797
- Publication date Apr 25, 2024
- Intel Corporation
- John A. Wiegert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCE...
- Publication number 20240111609
- Publication date Apr 4, 2024
- Intel Corporation
- Biju George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING
- Publication number 20240112295
- Publication date Apr 4, 2024
- Intel Corporation
- Biju George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINISTIC BROADCASTING FROM SHARED MEMORY
- Publication number 20240111534
- Publication date Apr 4, 2024
- Intel Corporation
- Fangwen Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ORDERED THREAD DISPATCH FOR THREAD TEAMS
- Publication number 20240111590
- Publication date Apr 4, 2024
- Intel Corporation
- Biju George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT
- Publication number 20240111826
- Publication date Apr 4, 2024
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH AWARE LRU CACHE REPLACEMENT POLICY
- Publication number 20240104025
- Publication date Mar 28, 2024
- Intel Corporation
- Biju George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ENHANCEMENTS FOR MATRIX LOAD/STORE INSTRUCTIONS
- Publication number 20240069914
- Publication date Feb 29, 2024
- Intel Corporation
- Biju George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MATRIX OPERATION OPTIMIZATION MECHANISM
- Publication number 20230289399
- Publication date Sep 14, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR MEMORY ACCESS ARCHITECTURE WITH ADDRESS SORTING
- Publication number 20230104845
- Publication date Apr 6, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Supporting 8-bit floating point format operands in a computing arch...

Architecture for block sparse operations on a systolic array

Dual pipeline parallel systolic array

Matrix operation optimization mechanism

Hierarchical thread scheduling based on multiple barriers

Dot product operations on sparse matrix elements

Lossless pixel compression based on inferred control information

Matrix operation optimization mechanism

Power-based and target-based graphics quality adjustment

MV/mode prediction, ROI-based transmit, metadata capture, and forma...

Selective coding

Power-based and target-based graphics quality adjustment

Mixed reality coding with overlays

Temporal motion vector prediction control in video coding

Techniques for hardware video encoding

Coding tools for subjective quality improvements in video codecs

Method and system of high throughput arithmetic entropy coding for...

Block level rate distortion optimized quantization

Temporal motion vector prediction control in video coding

MV/mode prediction, ROI-based transmit, metadata capture, and forma...

Mixed reality coding with overlays

Power-based and target-based graphics quality adjustment

Techniques for hardware video encoding

Method and system of entropy coding using look-up table based proba...

Motion estimation methods for residual prediction

Patents Applicationslast 30 patents

MULTIPLE REGISTER ALLOCATION SIZES FOR GPU HARDWARE THREADS

DUAL PIPELINE PARALLEL SYSTOLIC ARRAY

CONVERSION OPERATIONS AND SPECIAL VALUE USE CASES SUPPORTING 8-BIT...

SUPPORTING 8-BIT FLOATING POINT FORMAT FOR PARALLEL COMPUTING AND S...

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER T...

32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLI...

FLOATING-POINT CONVERSION VIA AN INTEGER UNIT

AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...

MATRIX OPERATION OPTIMIZATION MECHANISM

SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...

NAMED AND CLUSTER BARRIERS

BROADCAST ASYNCHRONOUS LOADS TO SHARED LOCAL MEMORY

SYNCHRONIZATION FOR DATA MULTICAST IN COMPUTE CORE CLUSTERS

SCALABLE AND CONFIGURABLE CLUSTERED SYSTOLIC ARRAY

DATA MULTICAST IN COMPUTE CORE CLUSTERS

CROSS-THREAD REGISTER SHARING FOR MATRIX MULTIPLICATION COMPUTE

ENHANCEMENTS FOR ACCUMULATOR USAGE AND INSTRUCTION FORWARDING IN MA...

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

NAMED AND CLUSTER BARRIERS

BROADCAST ASYNCHRONOUS LOADS TO SHARED LOCAL MEMORY

SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCE...

SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING

DETERMINISTIC BROADCASTING FROM SHARED MEMORY

ORDERED THREAD DISPATCH FOR THREAD TEAMS

HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT

PREFETCH AWARE LRU CACHE REPLACEMENT POLICY

HARDWARE ENHANCEMENTS FOR MATRIX LOAD/STORE INSTRUCTIONS

MATRIX OPERATION OPTIMIZATION MECHANISM

GRAPHICS PROCESSOR MEMORY ACCESS ARCHITECTURE WITH ADDRESS SORTING