Fangxing Wei

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Coarse delay lock estimation for digital DLL circuits
- Patent number 11,018,676
- Issue date May 25, 2021
- Intel Corporation
- Fangxing Wei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital phase control with programmable tracking slope having a pro...
- Patent number 10,574,241
- Issue date Feb 25, 2020
- Intel Corporation
- Fangxing Wei
- G11 - INFORMATION STORAGE
Information Patent Grant
Coarse delay lock estimation for digital DLL circuits
- Patent number 10,270,453
- Issue date Apr 23, 2019
- Intel Corporation
- Fangxing Wei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual-range clock duty cycle corrector
- Patent number 9,805,773
- Issue date Oct 31, 2017
- Intel Corporation
- Dan Shi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital phase control with programmable tracking slope
- Patent number 9,614,533
- Issue date Apr 4, 2017
- Intel Corporation
- Fangxing Wei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Glitch-free digitally controlled oscillator code update
- Patent number 9,548,747
- Issue date Jan 17, 2017
- Intel Corporation
- Fangxing Wei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
XOR (exclusive or) based triangular mixing for digital phase control
- Patent number 9,455,726
- Issue date Sep 27, 2016
- Intel Corporation
- Fangxing Wei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital delay-locked loop (DLL) training
- Patent number 9,407,273
- Issue date Aug 2, 2016
- Intel Corporation
- Fangxing Wei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Temperature compensation for oscillator
- Patent number 9,231,519
- Issue date Jan 5, 2016
- Intel Corporation
- Fangxing Wei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System timing margin improvement of high speed I/O interconnect lin...
- Patent number 9,166,773
- Issue date Oct 20, 2015
- Intel Corporation
- Fangxing Wei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Gated ring oscillator-based digital eye width monitor for high-spee...
- Patent number 9,112,671
- Issue date Aug 18, 2015
- Intel Corporation
- Fangxing Wei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System timing margin improvement of high speed I/O interconnect lin...
- Patent number 8,929,499
- Issue date Jan 6, 2015
- Intel Corporation
- Fangxing Wei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed serial link receiver with centrally controlled offset ca...
- Patent number 8,059,756
- Issue date Nov 15, 2011
- Intel Corporation
- Fangxing Wei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed serial link receiver with centrally controlled offset ca...
- Patent number 7,391,824
- Issue date Jun 24, 2008
- Intel Corporation
- Fangxing Wei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronized serial interface
- Patent number 7,249,273
- Issue date Jul 24, 2007
- Intel Corporation
- Chengting Zhao
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COARSE DELAY LOCK ESTIMATION FOR DIGITAL DLL CIRCUITS
- Publication number 20200007132
- Publication date Jan 2, 2020
- Intel Corporation
- Fangxing Wei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dual-Range Clock Duty Cycle Corrector
- Publication number 20170337952
- Publication date Nov 23, 2017
- Intel Corporation
- Dan Shi
- G11 - INFORMATION STORAGE
Information Patent Application
COARSE DELAY LOCK ESTIMATION FOR DIGITAL DLL CIRCUITS
- Publication number 20170288683
- Publication date Oct 5, 2017
- Intel Corporation
- Fangxing Wei
- G11 - INFORMATION STORAGE
Information Patent Application
DIGITAL PHASE CONTROL WITH PROGRAMMABLE TRACKING SLOPE
- Publication number 20170237444
- Publication date Aug 17, 2017
- Intel Corporation
- Fangxing Wei
- G11 - INFORMATION STORAGE
Information Patent Application
DIGITAL PHASE CONTROL WITH PROGRAMMABLE TRACKING SLOPE
- Publication number 20160373119
- Publication date Dec 22, 2016
- Intel Corporation
- Fangxing Wei
- G11 - INFORMATION STORAGE
Information Patent Application
GLITCH-FREE DIGITALLY CONTROLLED OSCILLATOR CODE UPDATE
- Publication number 20160336943
- Publication date Nov 17, 2016
- Intel Corporation
- FANGXING WEI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM TIMING MARGIN IMPROVEMENT OF HIGH SPEED I/O INTERCONNECT LIN...
- Publication number 20150124916
- Publication date May 7, 2015
- Intel Corporation
- Fangxing Wei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TEMPERATURE COMPENSATION FOR OSCILLATOR
- Publication number 20140218123
- Publication date Aug 7, 2014
- Fangxing Wei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
GATED RING OSCILLATOR-BASED DIGITAL EYE WIDTH MONITOR FOR HIGH-SPEE...
- Publication number 20140204988
- Publication date Jul 24, 2014
- Fangxing Wei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM TIMING MARGIN IMPROVEMENT OF HIGH SPEED I/O INTERCONNECT LIN...
- Publication number 20140093014
- Publication date Apr 3, 2014
- Fangxing Wei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIGH-SPEED SERIAL LINK RECEIVER WITH CENTRALLY CONTROLLED OFFSET CA...
- Publication number 20080224754
- Publication date Sep 18, 2008
- Intel Corporation
- Fangxing Wei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Synchronized serial interface
- Publication number 20040260961
- Publication date Dec 23, 2004
- Chengting Zhao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High-speed serial link receiver with centrally controlled offset ca...
- Publication number 20040234010
- Publication date Nov 25, 2004
- Intel Corporation
- Fangxing Wei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Fangxing Wei

Person

Patents Grantslast 30 patents

Coarse delay lock estimation for digital DLL circuits

Digital phase control with programmable tracking slope having a pro...

Coarse delay lock estimation for digital DLL circuits

Dual-range clock duty cycle corrector

Digital phase control with programmable tracking slope

Glitch-free digitally controlled oscillator code update

XOR (exclusive or) based triangular mixing for digital phase control

Digital delay-locked loop (DLL) training

Temperature compensation for oscillator

System timing margin improvement of high speed I/O interconnect lin...

Gated ring oscillator-based digital eye width monitor for high-spee...

System timing margin improvement of high speed I/O interconnect lin...

High-speed serial link receiver with centrally controlled offset ca...

High-speed serial link receiver with centrally controlled offset ca...

Synchronized serial interface

Patents Applicationslast 30 patents

COARSE DELAY LOCK ESTIMATION FOR DIGITAL DLL CIRCUITS

Dual-Range Clock Duty Cycle Corrector

COARSE DELAY LOCK ESTIMATION FOR DIGITAL DLL CIRCUITS

DIGITAL PHASE CONTROL WITH PROGRAMMABLE TRACKING SLOPE

DIGITAL PHASE CONTROL WITH PROGRAMMABLE TRACKING SLOPE

GLITCH-FREE DIGITALLY CONTROLLED OSCILLATOR CODE UPDATE

SYSTEM TIMING MARGIN IMPROVEMENT OF HIGH SPEED I/O INTERCONNECT LIN...

TEMPERATURE COMPENSATION FOR OSCILLATOR

GATED RING OSCILLATOR-BASED DIGITAL EYE WIDTH MONITOR FOR HIGH-SPEE...

SYSTEM TIMING MARGIN IMPROVEMENT OF HIGH SPEED I/O INTERCONNECT LIN...

HIGH-SPEED SERIAL LINK RECEIVER WITH CENTRALLY CONTROLLED OFFSET CA...

Synchronized serial interface

High-speed serial link receiver with centrally controlled offset ca...