Fangyun Richter

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Manufacture of interconnects for integration of multiple integrated...
- Patent number 10,541,205
- Issue date Jan 21, 2020
- Intel Corporation
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strain-enhanced transistors with adjustable layouts
- Patent number 9,634,094
- Issue date Apr 25, 2017
- Altera Corporation
- Girish Venkitachalam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit and a method to optimize strain inducing composites
- Patent number 9,484,411
- Issue date Nov 1, 2016
- Altera Corporation
- Girish Venkitachalam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-k dielectric device and process
- Patent number 9,166,045
- Issue date Oct 20, 2015
- Altera Coporation
- Che Ta Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal routing in advanced process technologies
- Patent number 9,099,531
- Issue date Aug 4, 2015
- Altera Corporation
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming gate structures for reduced leakage
- Patent number 8,921,217
- Issue date Dec 30, 2014
- Altera Corporation
- Wuu-Cherng Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for fabricating integrated circuits with patterned thermal a...
- Patent number 8,912,104
- Issue date Dec 16, 2014
- Altera Corporation
- Deepa Ratakonda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-k dielectric device and process
- Patent number 8,835,265
- Issue date Sep 16, 2014
- Altera Corporation
- Che Ta Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit and a method to optimize strain inducing composites
- Patent number 8,765,541
- Issue date Jul 1, 2014
- Altera Corporation
- Girish Venkitachalam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strain enhanced transistors with adjustable layouts
- Patent number 8,664,725
- Issue date Mar 4, 2014
- Altera Corporation
- Girish Venkitachalam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Density transition zones for integrated circuits
- Patent number 8,159,044
- Issue date Apr 17, 2012
- Altera Corporation
- Shuxian Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for reducing charge loss in a nonvolatile memo...
- Patent number 7,291,546
- Issue date Nov 6, 2007
- Altera Corporation
- Irfan Rahim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bipolar transistors with low base resistance for CMOS integrated ci...
- Patent number 7,285,454
- Issue date Oct 23, 2007
- Altera Corporation
- Minchang Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bipolar transistors with low base resistance for CMOS integrated ci...
- Patent number 6,972,466
- Issue date Dec 6, 2005
- Altera Corporation
- Minchang Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for reducing charge loss in a nonvolatile memo...
- Patent number 6,773,987
- Issue date Aug 10, 2004
- Altera Corporation
- Irfan Rahim
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHODS OF FORMING GATE STRUCTURES FOR REDUCED LEAKAGE
- Publication number 20130157451
- Publication date Jun 20, 2013
- Wuu-Cherng Lin
- G06 - COMPUTING CALCULATING COUNTING

Fangyun Richter

Person

Patents Grantslast 30 patents

Manufacture of interconnects for integration of multiple integrated...

Strain-enhanced transistors with adjustable layouts

Integrated circuit and a method to optimize strain inducing composites

High-k dielectric device and process

Metal routing in advanced process technologies

Methods of forming gate structures for reduced leakage

Method for fabricating integrated circuits with patterned thermal a...

High-k dielectric device and process

Integrated circuit and a method to optimize strain inducing composites

Strain enhanced transistors with adjustable layouts

Density transition zones for integrated circuits

Method and apparatus for reducing charge loss in a nonvolatile memo...

Bipolar transistors with low base resistance for CMOS integrated ci...

Bipolar transistors with low base resistance for CMOS integrated ci...

Method and apparatus for reducing charge loss in a nonvolatile memo...

Patents Applicationslast 30 patents

METHODS OF FORMING GATE STRUCTURES FOR REDUCED LEAKAGE