Farid A. Yazdy

Person

Belmont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for round trip delay measurement in a bi-direc...
- Patent number 7,286,527
- Issue date Oct 23, 2007
- Brocade Communications Systems, Inc.
- Farid A. Yazdy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hardware graphics accelerator having access to multiple types of me...
- Patent number 6,373,493
- Issue date Apr 16, 2002
- Apple Computer, Inc.
- Jay B. Rickard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache management during cache inhibited transactions for increasing...
- Patent number 6,256,710
- Issue date Jul 3, 2001
- Apple Computer, Inc.
- Farid A. Yazdy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address and data bus arbiter for pipelined transactions on a split bus
- Patent number 5,901,295
- Issue date May 4, 1999
- Apple Computer, Inc.
- Farid A. Yazdy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherency where multiple processors may access the same data...
- Patent number 5,845,327
- Issue date Dec 1, 1998
- Apple Computer, Inc.
- Jay B. Rickard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address bus arbiter for pipelined transactions on a split bus
- Patent number 5,815,676
- Issue date Sep 29, 1998
- Apple Computer, Inc.
- Farid A. Yazdy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address tenure control for cache management wherein bus master addr...
- Patent number 5,812,815
- Issue date Sep 22, 1998
- Apple Computer, Inc.
- Farid A. Yazdy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data bus arbiter for pipelined transactions on a split bus
- Patent number 5,708,783
- Issue date Jan 13, 1998
- Apple Computer, Inc.
- Farid A. Yazdy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for controlling back-to-back burst reads in a...
- Patent number 5,603,007
- Issue date Feb 11, 1997
- Apple Computer, Inc.
- Farid A. Yazdy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for translating incompatible bus transactions
- Patent number 5,600,802
- Issue date Feb 4, 1997
- Apple Computer, Inc.
- Farid A. Yazdy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bus arbiter for a computer system having a dsp co-processor
- Patent number 5,546,547
- Issue date Aug 13, 1996
- Apple Computer, Inc.
- Michael J. Bowes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peripheral processor card for upgrading a computer
- Patent number 5,515,514
- Issue date May 7, 1996
- Apple Computer, Inc.
- Michael J. Dhuey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for improved DRAM refresh operation
- Patent number 5,500,827
- Issue date Mar 19, 1996
- Apple Computer, Inc.
- Farid A. Yazdy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for selectively switching between input signals
- Patent number 5,237,573
- Issue date Aug 17, 1993
- Apple Computer, Inc.
- Michael J. Dhuey
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for round trip delay measurement in a bi-direc...
- Publication number 20040017806
- Publication date Jan 29, 2004
- Brocade Communications Systems, Inc.
- Farid A. Yazdy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Farid A. Yazdy

Person

Patents Grantslast 30 patents

Method and apparatus for round trip delay measurement in a bi-direc...

Hardware graphics accelerator having access to multiple types of me...

Cache management during cache inhibited transactions for increasing...

Address and data bus arbiter for pipelined transactions on a split bus

Cache coherency where multiple processors may access the same data...

Address bus arbiter for pipelined transactions on a split bus

Address tenure control for cache management wherein bus master addr...

Data bus arbiter for pipelined transactions on a split bus

Methods and apparatus for controlling back-to-back burst reads in a...

Methods and apparatus for translating incompatible bus transactions

Memory bus arbiter for a computer system having a dsp co-processor

Peripheral processor card for upgrading a computer

Method and apparatus for improved DRAM refresh operation

Method and apparatus for selectively switching between input signals

Patents Applicationslast 30 patents

Method and apparatus for round trip delay measurement in a bi-direc...