Farinaz Koushanfar

Person

Houston, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Synthetic human fingerprints
- Patent number 12,014,569
- Issue date Jun 18, 2024
- The Regents of the University of California
- Mohammad Sadegh Riazi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital watermarking of machine learning models
- Patent number 11,972,408
- Issue date Apr 30, 2024
- The Regents of the University of California
- Bita Darvish Rouhani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioned machine learning architecture
- Patent number 11,922,313
- Issue date Mar 5, 2024
- William Marsh Rice University
- Bita Darvish Rouhani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware-based machine learning acceleration
- Patent number 11,651,260
- Issue date May 16, 2023
- The Regents of the University of California
- Bita Darvish Rouhani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Small-world nets for fast neural network training and execution
- Patent number 11,625,614
- Issue date Apr 11, 2023
- The Regents of the University of California
- Mojan Javaheripi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, circuits and computer program products providing a framewo...
- Patent number 11,599,832
- Issue date Mar 7, 2023
- The Regents of the University of California
- Mohsen Imani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detection and prevention of adversarial deep learning
- Patent number 11,526,601
- Issue date Dec 13, 2022
- The Regents of the University of California
- Bita Darvish Rouhani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Training a machine learning model with limited training data
- Patent number 11,386,326
- Issue date Jul 12, 2022
- The Regents of the University of California
- Fang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PUF authentication and key-exchange by substring matching
- Patent number 9,628,272
- Issue date Apr 18, 2017
- William Marsh Rice University
- Masoud Rostami
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and systems of digital rights management for integrated cir...
- Patent number 8,966,660
- Issue date Feb 24, 2015
- William Marsh Rice University
- Farinaz Koushanfar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identification of integrated circuits
- Patent number 8,788,559
- Issue date Jul 22, 2014
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Miodrag Potkonjak
- G01 - MEASURING TESTING
Information Patent Grant
Protecting hardware circuit design by secret sharing
- Patent number 8,732,468
- Issue date May 20, 2014
- The Regents of the University of Michigan
- Jarrod A. Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware synthesis using thermally aware scheduling and binding
- Patent number 8,656,338
- Issue date Feb 18, 2014
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Farinaz Koushanfar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identification of integrated circuits
- Patent number 8,620,982
- Issue date Dec 31, 2013
- Empire Technology Development, LLC
- Miodrag Potkonjak
- G01 - MEASURING TESTING
Information Patent Grant
Input vector selection for reducing current leakage in integrated c...
- Patent number 8,443,034
- Issue date May 14, 2013
- Empire Technology Development, LLC
- Farinaz Koushanfar
- G01 - MEASURING TESTING
Information Patent Grant
Identification of integrated circuits
- Patent number 8,417,754
- Issue date Apr 9, 2013
- Empire Technology Development, LLC
- Miodrag Potkonjak
- G01 - MEASURING TESTING
Information Patent Grant
Controlling integrated circuits including remote activation or deac...
- Patent number 8,387,071
- Issue date Feb 26, 2013
- Empire Technology Development, LLC
- Miodrag Potkonjak
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Testing security of mapping functions
- Patent number 8,370,787
- Issue date Feb 5, 2013
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Farinaz Koushanfar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hardware synthesis using thermally aware scheduling and binding
- Patent number 8,365,131
- Issue date Jan 29, 2013
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Farinaz Koushanfar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for N-variant integrated circuit (IC) design, and IC having...
- Patent number 8,176,448
- Issue date May 8, 2012
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Farinaz Koushanfar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lightweight secure physically unclonable functions
- Patent number 8,054,098
- Issue date Nov 8, 2011
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Farinaz Koushanfar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Lightweight secure physically unclonable functions
- Patent number 7,898,283
- Issue date Mar 1, 2011
- Farinaz Koushanfar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
QUANTIZATION AND CRYPTOGRAPHIC PROTOCOL BASED MACHINE LEARNING MODE...
- Publication number 20250005200
- Publication date Jan 2, 2025
- The Regents of the University of California
- Mojan Javaheripi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO KNOWLEDGE PROOF OF DEEP NEURAL NETWORK OWNERSHIP
- Publication number 20240370535
- Publication date Nov 7, 2024
- The Regents of the University of California
- Nojan Sheybani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO PEEK ROBUSTNESS CHECKS FOR FEDERATED LEARNING
- Publication number 20240346379
- Publication date Oct 17, 2024
- The Regents of the University of California
- Zahra Ghodsi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL WATERMARKING OF MACHINE LEARNING MODELS
- Publication number 20240242191
- Publication date Jul 18, 2024
- The Regents of the University of California
- Bita Darvish Rouhani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNTHETIC HUMAN FINGERPRINTS
- Publication number 20230075233
- Publication date Mar 9, 2023
- The Regents of the University of California
- Mohammad Sadegh Riazi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OBLIVIOUS BINARY NEURAL NETWORKS
- Publication number 20220083865
- Publication date Mar 17, 2022
- The Regents of the University of California
- Mohammad Sadegh Riazi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITIONED MACHINE LEARNING ARCHITECTURE
- Publication number 20210295166
- Publication date Sep 23, 2021
- William Marsh Rice University
- Bita Darvish Rouhani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESIDUAL BINARY NEURAL NETWORK
- Publication number 20210166106
- Publication date Jun 3, 2021
- The Regents of the University of California
- Mohammad Ghasemzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL WATERMARKING OF MACHINE LEARNING MODELS
- Publication number 20210019605
- Publication date Jan 21, 2021
- The Regents of the University of California
- Bita Darvish Rouhani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PEER-TO-PEER TRAINING OF A MACHINE LEARNING MODEL
- Publication number 20210012196
- Publication date Jan 14, 2021
- The Regents of the University of California
- Anusha Lalitha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, CIRCUITS AND COMPUTER PROGRAM PRODUCTS PROVIDING A FRAMEWO...
- Publication number 20200410404
- Publication date Dec 31, 2020
- The Regents of the University of Californie
- Mohsen Imani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTION AND PREVENTION OF ADVERSARIAL DEEP LEARNING
- Publication number 20200167471
- Publication date May 28, 2020
- The Regents of the University of California
- Bita Darvish Rouhani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SMALL-WORLD NETS FOR FAST NEURAL NETWORK TRAINING AND EXECUTION
- Publication number 20200125960
- Publication date Apr 23, 2020
- The Regents of the University of California
- Mojan Javaheripi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE-BASED MACHINE LEARNING ACCELERATION
- Publication number 20200027016
- Publication date Jan 23, 2020
- The Regents of the University of California
- Bita Darvish Rouhani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAINING A MACHINE LEARNING MODEL WITH LIMITED TRAINING DATA
- Publication number 20190378015
- Publication date Dec 12, 2019
- The Regents of the University of California
- Fang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PUF Authentication and Key-Exchange by Substring Matching
- Publication number 20150195088
- Publication date Jul 9, 2015
- William Marsh Rice University
- Masoud Rostami
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
IDENTIFICATION OF INTEGRATED CIRCUITS
- Publication number 20140088892
- Publication date Mar 27, 2014
- Empire Technology Development, LLC
- MIODRAG POTKONJAK
- G01 - MEASURING TESTING
Information Patent Application
IDENTIFICATION OF INTEGRATED CIRCUITS
- Publication number 20130226477
- Publication date Aug 29, 2013
- Empire Technology Development, LLC
- MIODRAG POTKONJAK
- G01 - MEASURING TESTING
Information Patent Application
Hardware Synthesis Using Thermally Aware Scheduling And Binding
- Publication number 20130145335
- Publication date Jun 6, 2013
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Farinaz Koushanfar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE SYNTHESIS USING THERMALLY AWARE SCHEDULING AND BINDING
- Publication number 20110173581
- Publication date Jul 14, 2011
- Farinaz Koushanfar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIGHTWEIGHT SECURE PHYSICALLY UNCLONABLE FUNCTIONS
- Publication number 20110095782
- Publication date Apr 28, 2011
- Farinaz Koushanfar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING INTEGRATED CIRCUITS INCLUDING REMOTE ACTIVATION OR DEAC...
- Publication number 20110055851
- Publication date Mar 3, 2011
- Miodrag Potkonjak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING SECURITY OF MAPPING FUNCTIONS
- Publication number 20110055649
- Publication date Mar 3, 2011
- Farinaz Koushanfar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIGHTWEIGHT SECURE PHYSICALLY UNCLONABLE FUNCTIONS
- Publication number 20110050279
- Publication date Mar 3, 2011
- Farinaz Koushanfar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR N-VARIANT INTEGRATED CIRCUIT (IC) DESIGN, AND IC HAVING...
- Publication number 20100318945
- Publication date Dec 16, 2010
- Farinaz Koushanfar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INPUT VECTOR SELECTION FOR REDUCING CURRENT LEAKAGE IN INTEGRATED C...
- Publication number 20100308895
- Publication date Dec 9, 2010
- Farinaz Koushanfar
- G01 - MEASURING TESTING
Information Patent Application
Methods for Protecting Against Piracy of Integrated Circuits
- Publication number 20100284539
- Publication date Nov 11, 2010
- The Regents of the University of Michigan
- Jarrod A. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Protecting Hardware Circuit Design by Secret Sharing
- Publication number 20100287374
- Publication date Nov 11, 2010
- The Regents of the University of Michigan
- Jarrod A. Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFICATION OF INTEGRATED CIRCUITS
- Publication number 20100287604
- Publication date Nov 11, 2010
- Miodrag Potkonjak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS OF DIGITAL RIGHTS MANAGEMENT FOR INTEGRATED CIR...
- Publication number 20100122353
- Publication date May 13, 2010
- William Marsh Rice University
- Farinaz Koushanfar
- G06 - COMPUTING CALCULATING COUNTING

Farinaz Koushanfar

Person

Patents Grantslast 30 patents

Synthetic human fingerprints

Digital watermarking of machine learning models

Partitioned machine learning architecture

Hardware-based machine learning acceleration

Small-world nets for fast neural network training and execution

Systems, circuits and computer program products providing a framewo...

Detection and prevention of adversarial deep learning

Training a machine learning model with limited training data

PUF authentication and key-exchange by substring matching

Methods and systems of digital rights management for integrated cir...

Identification of integrated circuits

Protecting hardware circuit design by secret sharing

Hardware synthesis using thermally aware scheduling and binding

Identification of integrated circuits

Input vector selection for reducing current leakage in integrated c...

Identification of integrated circuits

Controlling integrated circuits including remote activation or deac...

Testing security of mapping functions

Hardware synthesis using thermally aware scheduling and binding

Method for N-variant integrated circuit (IC) design, and IC having...

Lightweight secure physically unclonable functions

Lightweight secure physically unclonable functions

Patents Applicationslast 30 patents

QUANTIZATION AND CRYPTOGRAPHIC PROTOCOL BASED MACHINE LEARNING MODE...

ZERO KNOWLEDGE PROOF OF DEEP NEURAL NETWORK OWNERSHIP

ZERO PEEK ROBUSTNESS CHECKS FOR FEDERATED LEARNING

DIGITAL WATERMARKING OF MACHINE LEARNING MODELS

SYNTHETIC HUMAN FINGERPRINTS

OBLIVIOUS BINARY NEURAL NETWORKS

PARTITIONED MACHINE LEARNING ARCHITECTURE

RESIDUAL BINARY NEURAL NETWORK

DIGITAL WATERMARKING OF MACHINE LEARNING MODELS

PEER-TO-PEER TRAINING OF A MACHINE LEARNING MODEL

SYSTEMS, CIRCUITS AND COMPUTER PROGRAM PRODUCTS PROVIDING A FRAMEWO...

DETECTION AND PREVENTION OF ADVERSARIAL DEEP LEARNING

SMALL-WORLD NETS FOR FAST NEURAL NETWORK TRAINING AND EXECUTION

HARDWARE-BASED MACHINE LEARNING ACCELERATION

TRAINING A MACHINE LEARNING MODEL WITH LIMITED TRAINING DATA

PUF Authentication and Key-Exchange by Substring Matching

IDENTIFICATION OF INTEGRATED CIRCUITS

IDENTIFICATION OF INTEGRATED CIRCUITS

Hardware Synthesis Using Thermally Aware Scheduling And Binding

HARDWARE SYNTHESIS USING THERMALLY AWARE SCHEDULING AND BINDING

LIGHTWEIGHT SECURE PHYSICALLY UNCLONABLE FUNCTIONS

CONTROLLING INTEGRATED CIRCUITS INCLUDING REMOTE ACTIVATION OR DEAC...

TESTING SECURITY OF MAPPING FUNCTIONS

LIGHTWEIGHT SECURE PHYSICALLY UNCLONABLE FUNCTIONS

METHOD FOR N-VARIANT INTEGRATED CIRCUIT (IC) DESIGN, AND IC HAVING...

INPUT VECTOR SELECTION FOR REDUCING CURRENT LEAKAGE IN INTEGRATED C...

Methods for Protecting Against Piracy of Integrated Circuits

Protecting Hardware Circuit Design by Secret Sharing

IDENTIFICATION OF INTEGRATED CIRCUITS

METHODS AND SYSTEMS OF DIGITAL RIGHTS MANAGEMENT FOR INTEGRATED CIR...