Farshad Ghahghahi

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor chip having stepped conductive pillars
- Patent number 11,955,447
- Issue date Apr 9, 2024
- Advanced Micro Devices, Inc.
- Suming Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit product customizations for identification code v...
- Patent number 11,315,883
- Issue date Apr 26, 2022
- Advanced Micro Devices, Inc.
- Suming Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-RDL structure packages and methods of fabricating the same
- Patent number 10,903,168
- Issue date Jan 26, 2021
- Advanced Micro Devices, Inc.
- Milind S. Bhagavat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-RDL structure packages and methods of fabricating the same
- Patent number 10,672,712
- Issue date Jun 2, 2020
- Advanced Micro Devices, Inc.
- Milind S. Bhagavat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ball grid array assignment
- Patent number 7,405,946
- Issue date Jul 29, 2008
- LSI Logic Corporation
- Jeffrey A. Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Robust high density substrate design for thermal cycling reliability
- Patent number 7,345,245
- Issue date Mar 18, 2008
- LSI Logic Corporation
- Anand Govind
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ball assignment system
- Patent number 7,319,272
- Issue date Jan 15, 2008
- LSI Logic Corporation
- Arun Ramakrishnan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Routing scheme for differential pairs in flip chip substrates
- Patent number 7,105,926
- Issue date Sep 12, 2006
- LSI Logic Corporation
- Arun Ramakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate via layout to improve bias humidity testing reliability
- Patent number 7,081,672
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Anand Govind
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Designing a ball assignment for a ball grid array package
- Patent number 7,051,434
- Issue date May 30, 2006
- LSI Logic Corporation
- Leah M. Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Measurement of package interconnect impedance using tester and supp...
- Patent number 6,946,866
- Issue date Sep 20, 2005
- LSI Logic Corporation
- Aritharan Thurairajaratnam
- G01 - MEASURING TESTING
Information Patent Grant
Stiffener design
- Patent number 6,825,066
- Issue date Nov 30, 2004
- LSI Logic Corporation
- Yogendra Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ball assignment for ball grid array package
- Patent number 6,762,366
- Issue date Jul 13, 2004
- LSI Logic Corporation
- Leah M. Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High density input output
- Patent number 6,671,865
- Issue date Dec 30, 2003
- LSI Logic Corporation
- Anwar Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microstrip package having optimized signal line impedance control
- Patent number 6,531,932
- Issue date Mar 11, 2003
- LSI Logic Corporation
- Anand Govind
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact escape pattern
- Patent number 6,479,319
- Issue date Nov 12, 2002
- LSI Logic Corporation
- Leonard L. Mora
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density signal routing
- Patent number 6,459,049
- Issue date Oct 1, 2002
- LSI Logic Corporation
- Leah M. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Irregular grid bond pad layout arrangement for a flip chip package
- Patent number 6,407,462
- Issue date Jun 18, 2002
- LSI Logic Corporation
- Nikon Banouvong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Routing density enhancement for semiconductor BGA packages and prin...
- Patent number 6,150,729
- Issue date Nov 21, 2000
- LSI Logic Corporation
- Farshad Ghahghahi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Misregistration fidutial
- Patent number 6,115,910
- Issue date Sep 12, 2000
- LSI Logic Corporation
- Farshad Ghahghahi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Thermally-enhanced flip chip IC package with extruded heatspreader
- Patent number 6,114,761
- Issue date Sep 5, 2000
- LSI Logic Corporation
- Atila Mertol
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR CHIP HAVING STEPPED CONDUCTIVE PILLARS
- Publication number 20240250051
- Publication date Jul 25, 2024
- ADVANCED MICRO DEVICES, INC.
- SUMING HU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP HAVING STEPPED CONDUCTIVE PILLARS
- Publication number 20230154878
- Publication date May 18, 2023
- ADVANCED MICRO DEVICES, INC.
- SUMING HU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CARRIER BOAT FOR DIE PACKAGE FLUX CLEANING
- Publication number 20230101770
- Publication date Mar 30, 2023
- ADVANCED MICRO DEVICES, INC.
- SUMING HU
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT PRODUCT CUSTOMIZATIONS FOR IDENTIFICATION CODE V...
- Publication number 20210143104
- Publication date May 13, 2021
- ADVANCED MICRO DEVICES, INC.
- Suming Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-RDL STRUCTURE PACKAGES AND METHODS OF FABRICATING THE SAME
- Publication number 20200294923
- Publication date Sep 17, 2020
- ADVANCED MICRO DEVICES, INC.
- Milind S. Bhagavat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-RDL STRUCTURE PACKAGES AND METHODS OF FABRICATING THE SAME
- Publication number 20200035606
- Publication date Jan 30, 2020
- Milind S. Bhagavat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ball grid array assignment
- Publication number 20060249302
- Publication date Nov 9, 2006
- LSI Logic Corporation
- Jeffrey A. Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Ball assignment system
- Publication number 20060223341
- Publication date Oct 5, 2006
- Arun Ramakrishnan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Routing scheme for differential pairs in flip chip substrates
- Publication number 20050110167
- Publication date May 26, 2005
- LSI Logic Corporation
- Arun Ramakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Robust high density substrate design for thermal cycling reliability
- Publication number 20050077081
- Publication date Apr 14, 2005
- Anand Govind
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Measurement of package interconnect impedance using tester and supp...
- Publication number 20040251925
- Publication date Dec 16, 2004
- Aritharan Thurairajaratnam
- G01 - MEASURING TESTING
Information Patent Application
Stiffener design
- Publication number 20040105241
- Publication date Jun 3, 2004
- Yogendra Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ball assignment for ball grid array package
- Publication number 20030183419
- Publication date Oct 2, 2003
- LSI Logic Corporation
- Leah M. Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Farshad Ghahghahi

Person

Patents Grantslast 30 patents

Semiconductor chip having stepped conductive pillars

Integrated circuit product customizations for identification code v...

Multi-RDL structure packages and methods of fabricating the same

Multi-RDL structure packages and methods of fabricating the same

Ball grid array assignment

Robust high density substrate design for thermal cycling reliability

Ball assignment system

Routing scheme for differential pairs in flip chip substrates

Substrate via layout to improve bias humidity testing reliability

Designing a ball assignment for a ball grid array package

Measurement of package interconnect impedance using tester and supp...

Stiffener design

Ball assignment for ball grid array package

High density input output

Microstrip package having optimized signal line impedance control

Contact escape pattern

High density signal routing

Irregular grid bond pad layout arrangement for a flip chip package

Routing density enhancement for semiconductor BGA packages and prin...

Misregistration fidutial

Thermally-enhanced flip chip IC package with extruded heatspreader

Patents Applicationslast 30 patents

SEMICONDUCTOR CHIP HAVING STEPPED CONDUCTIVE PILLARS

SEMICONDUCTOR CHIP HAVING STEPPED CONDUCTIVE PILLARS

CARRIER BOAT FOR DIE PACKAGE FLUX CLEANING

INTEGRATED CIRCUIT PRODUCT CUSTOMIZATIONS FOR IDENTIFICATION CODE V...

MULTI-RDL STRUCTURE PACKAGES AND METHODS OF FABRICATING THE SAME

MULTI-RDL STRUCTURE PACKAGES AND METHODS OF FABRICATING THE SAME

Ball grid array assignment

Ball assignment system

Routing scheme for differential pairs in flip chip substrates

Robust high density substrate design for thermal cycling reliability

Measurement of package interconnect impedance using tester and supp...

Stiffener design

Ball assignment for ball grid array package