Fatih Hamzaoglu

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Capacitor separations in dielectric layers
- Patent number 11,991,873
- Issue date May 21, 2024
- Intel Corporation
- Travis W. Lajoie
Information Patent Grant
Capacitor connections in dielectric layers
- Patent number 11,832,438
- Issue date Nov 28, 2023
- Intel Corporation
- Travis W. Lajoie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory architecture at back-end-of-line
- Patent number 11,690,212
- Issue date Jun 27, 2023
- Intel Corporation
- Umut Arslan
- G11 - INFORMATION STORAGE
Information Patent Grant
Intermediate separation layers at the back-end-of-line
- Patent number 11,652,047
- Issue date May 16, 2023
- Intel Corporation
- Travis W. Lajoie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor separations in dielectric layers
- Patent number 11,610,894
- Issue date Mar 21, 2023
- Intel Corporation
- Travis W. Lajoie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cells based on vertical thin-film transistors
- Patent number 11,462,541
- Issue date Oct 4, 2022
- Intel Corporation
- Juan G. Alzate Vinasco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked thin-film transistor based embedded dynamic random-access m...
- Patent number 11,450,669
- Issue date Sep 20, 2022
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip manufacturing process for integrating logic circ...
- Patent number 11,094,358
- Issue date Aug 17, 2021
- Intel Corporation
- Ilya Karpov
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for low power write and read operations for resistive memory
- Patent number 11,024,356
- Issue date Jun 1, 2021
- Intel Corporation
- Liqiong Wei
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods to control operations performed on resistiv...
- Patent number 10,515,697
- Issue date Dec 24, 2019
- Intel Corporation
- Pulkit Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for low power write and read operations for resistive memory
- Patent number 10,438,640
- Issue date Oct 8, 2019
- Intel Corporation
- Liqiong Wei
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for low power write and read operations for resistive memory
- Patent number 10,068,628
- Issue date Sep 4, 2018
- Intel Corporation
- Liqiong Wei
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell with improved write margin
- Patent number 9,978,447
- Issue date May 22, 2018
- Intel Corporation
- Yih Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive memory write circuitry with bit line drive strength based...
- Patent number 9,922,691
- Issue date Mar 20, 2018
- Intel Corporation
- Pulkit Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Low resistance bitline and sourceline apparatus for improving read...
- Patent number 9,865,322
- Issue date Jan 9, 2018
- Intel Corporation
- Cyrille Dray
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell with retention using resistive memory
- Patent number 9,805,790
- Issue date Oct 31, 2017
- Intel Corporation
- Nathaniel J. August
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for adjusting supply level to improve write margin of a m...
- Patent number 9,666,268
- Issue date May 30, 2017
- Intel Corporation
- Yih Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Low resistance bitline and sourceline apparatus for improving read...
- Patent number 9,478,273
- Issue date Oct 25, 2016
- Intel Corporation
- Cyrille Dray
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems to read a magnetic tunnel junction (MTJ) based...
- Patent number 9,455,011
- Issue date Sep 27, 2016
- Intel Corporation
- Arijit Raychowdhury
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile latch using spin-transfer torque memory device
- Patent number 9,330,747
- Issue date May 3, 2016
- Intel Corporation
- Yih Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for detecting write completion for resistiv...
- Patent number 9,286,976
- Issue date Mar 15, 2016
- Intel Corporation
- Blake Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive memory write circuitry with bit line drive strength based...
- Patent number 9,281,043
- Issue date Mar 8, 2016
- Intel Corporation
- Pulkit Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell with improved write margin
- Patent number 9,111,600
- Issue date Aug 18, 2015
- Intel Corporation
- Yih Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitline floating during non-access mode for memory arrays
- Patent number 8,982,659
- Issue date Mar 17, 2015
- Intel Corporation
- Tsung-Yung Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Nor logic word line selection
- Patent number 8,547,777
- Issue date Oct 1, 2013
- Intel Corporation
- Swaroop Ghosh
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND logic word line selection
- Patent number 8,456,946
- Issue date Jun 4, 2013
- Intel Corporation
- Swaroop Ghosh
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive and dynamic stability enhancement for memories
- Patent number 8,451,670
- Issue date May 28, 2013
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical DRAM sensing
- Patent number 8,406,073
- Issue date Mar 26, 2013
- Intel Corporation
- Dinesh Somasekhar
- G11 - INFORMATION STORAGE
Information Patent Grant
Cache leakage shut-off mechanism
- Patent number 7,657,767
- Issue date Feb 2, 2010
- Intel Corporation
- Stefan Rusu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with dynamically adjustable supply
- Patent number 7,403,426
- Issue date Jul 22, 2008
- Intel Corporation
- Fatih Hamzaoglu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CAPACITOR CONNECTIONS IN DIELECTRIC LAYERS
- Publication number 20240049450
- Publication date Feb 8, 2024
- Intel Corporation
- Travis W. LAJOIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE WITH PERIPHERAL CIRCUITRY WHICH EXTENDS UNDER A BACK...
- Publication number 20230397410
- Publication date Dec 7, 2023
- Intel Corporation
- Pulkit Jain
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-TIER MEMORY STRUCTURE WITH GRADED CHARACTERISTICS
- Publication number 20230371233
- Publication date Nov 16, 2023
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITOR SEPARATIONS IN DIELECTRIC LAYERS
- Publication number 20230200043
- Publication date Jun 22, 2023
- Intel Corporation
- Travis W. LAJOIE
Information Patent Application
TWO TRANSISTOR MEMORY CELL USING STACKED THIN-FILM TRANSISTORS
- Publication number 20230171936
- Publication date Jun 1, 2023
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
BILAYER MEMORY STACKING WITH LINES SHARED BETWEEN BOTTOM AND TOP ME...
- Publication number 20230067765
- Publication date Mar 2, 2023
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DECOUPLING CAPACITORS AND METHODS OF FABRICATION
- Publication number 20220415896
- Publication date Dec 29, 2022
- Intel Corporation
- Juan G. Alzate-Vinasco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKEND MEMORY WITH AIR GAPS IN UPPER METAL LAYERS
- Publication number 20220406782
- Publication date Dec 22, 2022
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITOR SEPARATIONS IN DIELECTRIC LAYERS
- Publication number 20200411520
- Publication date Dec 31, 2020
- Intel Corporation
- Travis W. LAJOIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY ARCHITECTURE AT BACK-END-OF-LINE
- Publication number 20200411524
- Publication date Dec 31, 2020
- Intel Corporation
- Umut ARSLAN
- G11 - INFORMATION STORAGE
Information Patent Application
INTERMEDIATE SEPARATION LAYERS AT THE BACK-END-OF-LINE
- Publication number 20200411426
- Publication date Dec 31, 2020
- Intel Corporation
- Travis W. LAJOIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AIR GAPS AND CAPACITORS IN DIELECTRIC LAYERS
- Publication number 20200411635
- Publication date Dec 31, 2020
- Intel Corporation
- Travis W. LAJOIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITOR CONNECTIONS IN DIELECTRIC LAYERS
- Publication number 20200411525
- Publication date Dec 31, 2020
- Intel Corporation
- Travis W. LAJOIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELLS BASED ON VERTICAL THIN-FILM TRANSISTORS
- Publication number 20200194434
- Publication date Jun 18, 2020
- Juan G. ALZATE VINASCO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO TRANSISTOR MEMORY CELL USING STACKED THIN-FILM TRANSISTORS
- Publication number 20200091156
- Publication date Mar 19, 2020
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED THIN-FILM TRANSISTOR BASED EMBEDDED DYNAMIC RANDOM-ACCESS M...
- Publication number 20200035683
- Publication date Jan 30, 2020
- Inte Corpooration
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY
- Publication number 20200020378
- Publication date Jan 16, 2020
- Intel Corporation
- Liqiong WEI
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS TO CONTROL OPERATIONS PERFORMED ON RESISTIV...
- Publication number 20200005866
- Publication date Jan 2, 2020
- Intel Corporation
- Pulkit Jain
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR CHIP MANUFACTURING PROCESS FOR INTEGRATING LOGIC CIRC...
- Publication number 20190279697
- Publication date Sep 12, 2019
- Intel Corporation
- Ilya KARPOV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY
- Publication number 20180342277
- Publication date Nov 29, 2018
- Intel Corporation
- Liqiong WEI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL WITH IMPROVED WRITE MARGIN
- Publication number 20170229166
- Publication date Aug 10, 2017
- Intel Corporation
- Yih WANG
- G11 - INFORMATION STORAGE
Information Patent Application
RESISTIVE MEMORY WRITE CIRCUITRY WITH BIT LINE DRIVE STRENGTH BASED...
- Publication number 20170047105
- Publication date Feb 16, 2017
- PULKIT JAIN
- G11 - INFORMATION STORAGE
Information Patent Application
LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ...
- Publication number 20170018298
- Publication date Jan 19, 2017
- Intel Corporation
- Cyrille Dray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL WITH RETENTION USING RESISTIVE MEMORY
- Publication number 20160232968
- Publication date Aug 11, 2016
- Intel Corporation
- Nathaniel J. AUGUST
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY
- Publication number 20160125927
- Publication date May 5, 2016
- Intel Corporation
- Liqiong WEI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL WITH IMPROVED WRITE MARGIN
- Publication number 20150235696
- Publication date Aug 20, 2015
- Yih Wang
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND SYSTEMS TO READ A MAGNETIC TUNNEL JUNCTION (MTJ) BASED...
- Publication number 20150206564
- Publication date Jul 23, 2015
- Arijit Raychowdhury
- G11 - INFORMATION STORAGE
Information Patent Application
LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ...
- Publication number 20150117095
- Publication date Apr 30, 2015
- Cyrille Dray
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE LATCH USING SPIN-TRANSFER TORQUE MEMORY DEVICE
- Publication number 20140340957
- Publication date Nov 20, 2014
- Yih WANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL WITH IMPROVED WRITE MARGIN
- Publication number 20140003181
- Publication date Jan 2, 2014
- Yih Wang
- G11 - INFORMATION STORAGE

Fatih Hamzaoglu

Person

Patents Grantslast 30 patents

Capacitor separations in dielectric layers

Capacitor connections in dielectric layers

Memory architecture at back-end-of-line

Intermediate separation layers at the back-end-of-line

Capacitor separations in dielectric layers

Memory cells based on vertical thin-film transistors

Stacked thin-film transistor based embedded dynamic random-access m...

Semiconductor chip manufacturing process for integrating logic circ...

Apparatus for low power write and read operations for resistive memory

Apparatuses and methods to control operations performed on resistiv...

Apparatus for low power write and read operations for resistive memory

Apparatus for low power write and read operations for resistive memory

Memory cell with improved write margin

Resistive memory write circuitry with bit line drive strength based...

Low resistance bitline and sourceline apparatus for improving read...

Memory cell with retention using resistive memory

Apparatus for adjusting supply level to improve write margin of a m...

Low resistance bitline and sourceline apparatus for improving read...

Methods and systems to read a magnetic tunnel junction (MTJ) based...

Non-volatile latch using spin-transfer torque memory device

Apparatuses and methods for detecting write completion for resistiv...

Resistive memory write circuitry with bit line drive strength based...

Memory cell with improved write margin

Bitline floating during non-access mode for memory arrays

Nor logic word line selection

NAND logic word line selection

Adaptive and dynamic stability enhancement for memories

Hierarchical DRAM sensing

Cache leakage shut-off mechanism

Memory with dynamically adjustable supply

Patents Applicationslast 30 patents

CAPACITOR CONNECTIONS IN DIELECTRIC LAYERS

MEMORY DEVICE WITH PERIPHERAL CIRCUITRY WHICH EXTENDS UNDER A BACK...

MULTI-TIER MEMORY STRUCTURE WITH GRADED CHARACTERISTICS

CAPACITOR SEPARATIONS IN DIELECTRIC LAYERS

TWO TRANSISTOR MEMORY CELL USING STACKED THIN-FILM TRANSISTORS

BILAYER MEMORY STACKING WITH LINES SHARED BETWEEN BOTTOM AND TOP ME...

DECOUPLING CAPACITORS AND METHODS OF FABRICATION

BACKEND MEMORY WITH AIR GAPS IN UPPER METAL LAYERS

CAPACITOR SEPARATIONS IN DIELECTRIC LAYERS

MEMORY ARCHITECTURE AT BACK-END-OF-LINE

INTERMEDIATE SEPARATION LAYERS AT THE BACK-END-OF-LINE

AIR GAPS AND CAPACITORS IN DIELECTRIC LAYERS

CAPACITOR CONNECTIONS IN DIELECTRIC LAYERS

MEMORY CELLS BASED ON VERTICAL THIN-FILM TRANSISTORS

TWO TRANSISTOR MEMORY CELL USING STACKED THIN-FILM TRANSISTORS

STACKED THIN-FILM TRANSISTOR BASED EMBEDDED DYNAMIC RANDOM-ACCESS M...

APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY

APPARATUSES AND METHODS TO CONTROL OPERATIONS PERFORMED ON RESISTIV...

SEMICONDUCTOR CHIP MANUFACTURING PROCESS FOR INTEGRATING LOGIC CIRC...

APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY

MEMORY CELL WITH IMPROVED WRITE MARGIN

RESISTIVE MEMORY WRITE CIRCUITRY WITH BIT LINE DRIVE STRENGTH BASED...

LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ...

MEMORY CELL WITH RETENTION USING RESISTIVE MEMORY

APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY

MEMORY CELL WITH IMPROVED WRITE MARGIN

METHODS AND SYSTEMS TO READ A MAGNETIC TUNNEL JUNCTION (MTJ) BASED...

LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ...

NON-VOLATILE LATCH USING SPIN-TRANSFER TORQUE MEMORY DEVICE

MEMORY CELL WITH IMPROVED WRITE MARGIN