Fei Su

Person

Ann Arbor, MI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Test architecture for die to die interconnect for three dimensional...
- Patent number 11,257,560
- Issue date Feb 22, 2022
- Intel Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Grant
Distributed error and anomaly communication architecture for analog...
- Patent number 10,929,337
- Issue date Feb 23, 2021
- Intel Corporation
- Rahul Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analog functional safety with anomaly detection
- Patent number 10,685,159
- Issue date Jun 16, 2020
- Intel Corporation
- Fei Su
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY BUILT-IN SELF-TEST (MBIST) AND BIST ADAPTIVE PORT (BAP) FOR...
- Publication number 20250218527
- Publication date Jul 3, 2025
- Intel Corporation
- Rakesh Kandula
- G11 - INFORMATION STORAGE
Information Patent Application
PREDICTIVE AND ADAPTIVE INFIELD TESTING BASED ON SILICON HEALTH INF...
- Publication number 20250172611
- Publication date May 29, 2025
- Intel Corporation
- Rakesh Kandula
- G01 - MEASURING TESTING
Information Patent Application
DEVICE, METHOD AND SYSTEM FOR IN-FIELD LANE TESTING AND REPAIR WITH...
- Publication number 20250052809
- Publication date Feb 13, 2025
- Intel Corporation
- Fei Su
- G01 - MEASURING TESTING
Information Patent Application
INTELLIGENT SENSORS FOR HIGH QUALITY SILICON LIFE CYCLE MANAGEMENT...
- Publication number 20240220312
- Publication date Jul 4, 2024
- Intel Corporation
- Rakesh Kandula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY AND COMPUTE-EFFICIENT UNSUPERVISED ANOMALY DETECTION FOR INT...
- Publication number 20220365523
- Publication date Nov 17, 2022
- Intel Corporation
- Fei Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED ERROR AND ANOMALY COMMUNICATION ARCHITECTURE FOR ANALOG...
- Publication number 20190361839
- Publication date Nov 28, 2019
- Intel Corporation
- Rahul Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN FOR TEST ARCHITECTURE FOR DIE TO DIE INTERCONNECT FOR THREE...
- Publication number 20190096503
- Publication date Mar 28, 2019
- Intel Corporation
- Sreejit CHAKRAVARTY
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ANALOG FUNCTIONAL SAFETY WITH ANOMALY DETECTION
- Publication number 20190050515
- Publication date Feb 14, 2019
- Intel Corporation
- Fei Su
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Test architecture for die to die interconnect for three dimensional...

Distributed error and anomaly communication architecture for analog...

Analog functional safety with anomaly detection

Patents Applicationslast 30 patents

MEMORY BUILT-IN SELF-TEST (MBIST) AND BIST ADAPTIVE PORT (BAP) FOR...

PREDICTIVE AND ADAPTIVE INFIELD TESTING BASED ON SILICON HEALTH INF...

DEVICE, METHOD AND SYSTEM FOR IN-FIELD LANE TESTING AND REPAIR WITH...

INTELLIGENT SENSORS FOR HIGH QUALITY SILICON LIFE CYCLE MANAGEMENT...

MEMORY AND COMPUTE-EFFICIENT UNSUPERVISED ANOMALY DETECTION FOR INT...

DISTRIBUTED ERROR AND ANOMALY COMMUNICATION ARCHITECTURE FOR ANALOG...

DESIGN FOR TEST ARCHITECTURE FOR DIE TO DIE INTERCONNECT FOR THREE...

ANALOG FUNCTIONAL SAFETY WITH ANOMALY DETECTION