Fidel Muradali

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Adaptive test time reduction for wafer-level testing
- Patent number 7,863,923
- Issue date Jan 4, 2011
- National Semiconductor Corporation
- Fidel Muradali
- G01 - MEASURING TESTING
Information Patent Grant
Adaptive test time reduction for wafer-level testing
- Patent number 7,626,412
- Issue date Dec 1, 2009
- National Semiconductor Corporation
- Fidel Muradali
- G01 - MEASURING TESTING
Information Patent Grant
Technique for debugging an integrated circuit having a parallel sca...
- Patent number 6,941,498
- Issue date Sep 6, 2005
- Agilent Technologies, Inc.
- Ismed D. S. Hartano
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical creation of vectors for quiescent current (IDDQ) tests...
- Patent number 6,751,768
- Issue date Jun 15, 2004
- Agilent Technologies, Inc.
- Fidel Muradali
- G01 - MEASURING TESTING
Information Patent Grant
Monitor circuitry and method for testing analog and/or mixed signal...
- Patent number 6,714,036
- Issue date Mar 30, 2004
- Agilent Technologies, Inc.
- Joan Figueras
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with scan test structure
- Patent number 6,587,981
- Issue date Jul 1, 2003
- Agilent Technologies, Inc.
- Fidel Muradali
- G01 - MEASURING TESTING
Information Patent Grant
Modular embedded test system for use in integrated circuits
- Patent number 6,191,603
- Issue date Feb 20, 2001
- Agilent Technologies Inc.
- Fidel Muradali
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
ADAPTIVE TEST TIME REDUCTION FOR WAFER-LEVEL TESTING
- Publication number 20100052725
- Publication date Mar 4, 2010
- National Semiconductor Corporation
- Fidel Muradali
- G01 - MEASURING TESTING
Information Patent Application
Adaptive test time reduction for wafer-level testing
- Publication number 20090058451
- Publication date Mar 5, 2009
- Fidel Muradali
- G01 - MEASURING TESTING
Information Patent Application
Functional test design for testability (DFT) and test architecture...
- Publication number 20050138500
- Publication date Jun 23, 2005
- Chimsong Sul
- G01 - MEASURING TESTING
Information Patent Application
Concurrent I/O
- Publication number 20050114733
- Publication date May 26, 2005
- Chimsong Sul
- G01 - MEASURING TESTING
Information Patent Application
MONITOR CIRCUITRY AND METHOD FOR TESTING ANALOG AND/OR MIXED SIGNAL...
- Publication number 20040008049
- Publication date Jan 15, 2004
- Joan Figueras
- G01 - MEASURING TESTING
Information Patent Application
Technique for debugging an integrated circuit having a parallel sca...
- Publication number 20030172334
- Publication date Sep 11, 2003
- Ismed D.S. Hartano
- G01 - MEASURING TESTING
Information Patent Application
Hierarchical creation of vectors for quiescent current (IDDQ) tests...
- Publication number 20030101398
- Publication date May 29, 2003
- Fidel Muradali
- G01 - MEASURING TESTING

Fidel Muradali

Person

Patents Grantslast 30 patents

Adaptive test time reduction for wafer-level testing

Adaptive test time reduction for wafer-level testing

Technique for debugging an integrated circuit having a parallel sca...

Hierarchical creation of vectors for quiescent current (IDDQ) tests...

Monitor circuitry and method for testing analog and/or mixed signal...

Integrated circuit with scan test structure

Modular embedded test system for use in integrated circuits

Patents Applicationslast 30 patents

ADAPTIVE TEST TIME REDUCTION FOR WAFER-LEVEL TESTING

Adaptive test time reduction for wafer-level testing

Functional test design for testability (DFT) and test architecture...

Concurrent I/O

MONITOR CIRCUITRY AND METHOD FOR TESTING ANALOG AND/OR MIXED SIGNAL...

Technique for debugging an integrated circuit having a parallel sca...

Hierarchical creation of vectors for quiescent current (IDDQ) tests...