Florian Cacho

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Grenoble, FR

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Patents Grantslast 30 patents

Information Patent Grant
Flip flop of a digital electronic chip
- Patent number 10,585,143
- Issue date Mar 10, 2020
- STMicroelectronics International N.V.
- Pascal Urard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for integrated circuit body biasing
- Patent number 10,050,037
- Issue date Aug 14, 2018
- STMicroelectronics S.A.
- Florian Cacho
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
FLIP FLOP OF A DIGITAL ELECTRONIC CHIP
- Publication number 20190018062
- Publication date Jan 17, 2019
- STMicroelectronics S.A.
- Pascal URARD
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND CIRCUIT FOR INTEGRATED CIRCUIT BODY BIASING
- Publication number 20180323196
- Publication date Nov 8, 2018
- STMicroelectronics S.A.
- Florian Cacho
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND CIRCUIT FOR INTEGRATED CIRCUIT BODY BIASING
- Publication number 20180130803
- Publication date May 10, 2018
- STMicroelectronics S.A.
- Florian Cacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROJUNCTION BIPOLAR TRANSISTOR RELIABILITY SIMULATION METHOD
- Publication number 20150142410
- Publication date May 21, 2015
- STMicroelectronics S.A.
- Salim Ighilahriz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SILICIDATION PROCESS FOR AN NMOS TRANSISTOR AND CORRESPONDING INTEG...
- Publication number 20070034948
- Publication date Feb 15, 2007
- STMicroelectronics (Crolles 2) SAS
- Florian Cacho
- H01 - BASIC ELECTRIC ELEMENTS