Francisco Adolfo Cano

Person

Sugar Land, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Screening of memory circuits
- Patent number 11,881,275
- Issue date Jan 23, 2024
- Texas Instruments Incorporated
- Francisco Adolfo Cano
- G11 - INFORMATION STORAGE
Information Patent Grant
Stress reduction on stacked transistor circuits
- Patent number 11,831,309
- Issue date Nov 28, 2023
- Texas Instruments Incorporated
- Erkan Bilhan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Stress reduction on stacked transistor circuits
- Patent number 11,626,875
- Issue date Apr 11, 2023
- Texas Instruments Incorporated
- Erkan Bilhan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Screening of memory circuits
- Patent number 11,568,951
- Issue date Jan 31, 2023
- Texas Instruments Incorporated
- Francisco Adolfo Cano
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits and methods for asymmetric aging prevention
- Patent number 8,890,588
- Issue date Nov 18, 2014
- Texas Instruments Incorporated
- Kalpesh Amrutlal Shah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compensatory memory system
- Patent number 8,144,533
- Issue date Mar 27, 2012
- Texas Instruments Incorporated
- Francisco A. Cano
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device testing
- Patent number 7,446,552
- Issue date Nov 4, 2008
- Texas Instruments Incorporated
- Francisco Cano
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device testing
- Patent number 7,446,553
- Issue date Nov 4, 2008
- Texas Instruments Incorporated
- Francisco Cano
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device testing
- Patent number 7,382,147
- Issue date Jun 3, 2008
- Texas Instruments Incorporated
- Francisco Cano
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device testing
- Patent number 7,365,556
- Issue date Apr 29, 2008
- Texas Instruments Incorporated
- Francisco Cano
- G01 - MEASURING TESTING
Information Patent Grant
Method for power routing and distribution in an integrated circuit...
- Patent number 6,581,201
- Issue date Jun 17, 2003
- Texas Instruments Incorporated
- Francisco A. Cano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for altering timing relationships of non-overl...
- Patent number 6,381,704
- Issue date Apr 30, 2002
- Texas Instruments Incorporated
- Francisco A. Cano
- G01 - MEASURING TESTING
Information Patent Grant
Method for hierarchical parasitic extraction of a CMOS design
- Patent number 6,363,516
- Issue date Mar 26, 2002
- Texas Instruments Incorporated
- Francisco A. Cano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for power routing and distribution in an integrated circuit...
- Patent number 6,308,307
- Issue date Oct 23, 2001
- Texas Instruments Incorporated
- Francisco A. Cano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for analyzing circuit delays caused by capacitive coupling i...
- Patent number 6,253,359
- Issue date Jun 26, 2001
- Texas Instruments Incorporated
- Francisco A. Cano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for determining signal line interconnect width...
- Patent number 6,038,383
- Issue date Mar 14, 2000
- Texas Instruments Incorporated
- Duane J. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing failures due to bit line coupling...
- Patent number 5,835,421
- Issue date Nov 10, 1998
- Texas Instruments Incorporated
- Luat Q. Pham
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for self-timed precharge of bit lines in a memory
- Patent number 5,745,421
- Issue date Apr 28, 1998
- Texas Instruments Incorporated
- Luat Q. Pham
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
STRESS REDUCTION ON STACKED TRANSISTOR CIRCUITS
- Publication number 20240088896
- Publication date Mar 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Erkan BILHAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRANSIENT CURRENT MANAGEMENT
- Publication number 20240037180
- Publication date Feb 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Donald E. STEISS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRESS REDUCTION ON STACKED TRANSISTOR CIRCUITS
- Publication number 20230238959
- Publication date Jul 27, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Erkan BILHAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCREENING OF MEMORY CIRCUITS
- Publication number 20230146764
- Publication date May 11, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Francisco Adolfo CANO
- G11 - INFORMATION STORAGE
Information Patent Application
SCREENING OF MEMORY CIRCUITS
- Publication number 20200294614
- Publication date Sep 17, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Francisco Adolfo CANO
- G11 - INFORMATION STORAGE
Information Patent Application
STRESS REDUCTION ON STACKED TRANSISTOR CIRCUITS
- Publication number 20190326910
- Publication date Oct 24, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Erkan BILHAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STRESS REDUCTION ON STACKED TRANSISTOR CIRCUITS
- Publication number 20190326909
- Publication date Oct 24, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Erkan BILHAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADAPTIVE VOLTAGE SCALING USING TEMPERATURE AND PERFORMANCE SENSORS
- Publication number 20190229732
- Publication date Jul 25, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Jose Luis Flores
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITS AND METHODS FOR ASYMMETRIC AGING PREVENTION
- Publication number 20140292383
- Publication date Oct 2, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Kalpesh Amrutlal Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Simplified Adaptive Voltage Scaling Using Lookup-Table and Analog T...
- Publication number 20140159800
- Publication date Jun 12, 2014
- Jose Luis Flores
- G01 - MEASURING TESTING
Information Patent Application
Performance Adaptive Voltage Scaling with Performance Tracking Sensor
- Publication number 20140159801
- Publication date Jun 12, 2014
- Jose Luis Flores
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS
- Publication number 20130002297
- Publication date Jan 3, 2013
- Texas Instruments, Incorporated
- Palkesh Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COHERENT ANALYSIS OF ASYMMETRIC AGING AND STATISTICAL PROCESS VARIA...
- Publication number 20120266123
- Publication date Oct 18, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Palkesh JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compensatory Memory System
- Publication number 20100265779
- Publication date Oct 21, 2010
- Francisco A. Cano
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor Device Testing
- Publication number 20070285104
- Publication date Dec 13, 2007
- Francisco Cano
- G01 - MEASURING TESTING
Information Patent Application
Semiconductor Device Testing
- Publication number 20070162808
- Publication date Jul 12, 2007
- Francisco Cano
- G01 - MEASURING TESTING
Information Patent Application
Semiconductor Device Testing
- Publication number 20070145999
- Publication date Jun 28, 2007
- Francisco Cano
- G01 - MEASURING TESTING
Information Patent Application
Semiconductor device testing
- Publication number 20060044001
- Publication date Mar 2, 2006
- Francisco Cano
- G01 - MEASURING TESTING
Information Patent Application
Method for power routing and distribution in an integrated circuit...
- Publication number 20020013931
- Publication date Jan 31, 2002
- Francisco A. Cano
- G06 - COMPUTING CALCULATING COUNTING

Francisco Adolfo Cano

Person

Patents Grantslast 30 patents

Screening of memory circuits

Stress reduction on stacked transistor circuits

Stress reduction on stacked transistor circuits

Screening of memory circuits

Circuits and methods for asymmetric aging prevention

Compensatory memory system

Semiconductor device testing

Semiconductor device testing

Semiconductor device testing

Semiconductor device testing

Method for power routing and distribution in an integrated circuit...

Method and apparatus for altering timing relationships of non-overl...

Method for hierarchical parasitic extraction of a CMOS design

Method for power routing and distribution in an integrated circuit...

Method for analyzing circuit delays caused by capacitive coupling i...

Method and apparatus for determining signal line interconnect width...

Method and apparatus for reducing failures due to bit line coupling...

Method and apparatus for self-timed precharge of bit lines in a memory

Patents Applicationslast 30 patents

STRESS REDUCTION ON STACKED TRANSISTOR CIRCUITS

TRANSIENT CURRENT MANAGEMENT

STRESS REDUCTION ON STACKED TRANSISTOR CIRCUITS

SCREENING OF MEMORY CIRCUITS

SCREENING OF MEMORY CIRCUITS

STRESS REDUCTION ON STACKED TRANSISTOR CIRCUITS

STRESS REDUCTION ON STACKED TRANSISTOR CIRCUITS

ADAPTIVE VOLTAGE SCALING USING TEMPERATURE AND PERFORMANCE SENSORS

CIRCUITS AND METHODS FOR ASYMMETRIC AGING PREVENTION

Simplified Adaptive Voltage Scaling Using Lookup-Table and Analog T...

Performance Adaptive Voltage Scaling with Performance Tracking Sensor

BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS

COHERENT ANALYSIS OF ASYMMETRIC AGING AND STATISTICAL PROCESS VARIA...

Compensatory Memory System

Semiconductor Device Testing

Semiconductor Device Testing

Semiconductor Device Testing

Semiconductor device testing

Method for power routing and distribution in an integrated circuit...