Franciscus P. J. M. Welten

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Eindhoven, NL

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Patents Grantslast 30 patents

Information Patent Grant
Logic full adder circuit
- Patent number 4,730,266
- Issue date Mar 8, 1988
- U.S. Philips Corporation
- Jozef L. van Meerbergen
- G06 - COMPUTING CALCULATING COUNTING