Francois Andrieu

Person

Saint-Ismier, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Device comprising wrap-gate transistors and method of manufacturing...
- Patent number 11,889,704
- Issue date Jan 30, 2024
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Sylvain Barraud
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Image sensor formed in sequential 3D technology
- Patent number 11,888,007
- Issue date Jan 30, 2024
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Lina Kadura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a semiconductor substrate having a stressed s...
- Patent number 11,810,789
- Issue date Nov 7, 2023
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Shay Reboh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resistive 3D memory
- Patent number 11,653,506
- Issue date May 16, 2023
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- François Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a microelectronic device
- Patent number 11,631,609
- Issue date Apr 18, 2023
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Heimanu Niebojewski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D memory and manufacturing process
- Patent number 11,532,670
- Issue date Dec 20, 2022
- Commissariat A'Lenergie Atomique et aux Energies Alternatives
- Sylvain Barraud
- G11 - INFORMATION STORAGE
Information Patent Grant
3D circuit provided with mesa isolation for the ground plane zone
- Patent number 11,139,209
- Issue date Oct 5, 2021
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Perrine Batude
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Assembly for 3D circuit with superposed transistor levels
- Patent number 11,024,544
- Issue date Jun 1, 2021
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Production of a 3D circuit with upper level transistor provided wit...
- Patent number 11,011,425
- Issue date May 18, 2021
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Perrine Batude
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit chip with strained NMOS and PMOS transistors
- Patent number 10,777,680
- Issue date Sep 15, 2020
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D SRAM circuit with double gate transistors with improved layout
- Patent number 10,741,565
- Issue date Aug 11, 2020
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- G11 - INFORMATION STORAGE
Information Patent Grant
3D circuit transistors with flipped gate
- Patent number 10,651,202
- Issue date May 12, 2020
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optimized double-gate transistors and fabricating process
- Patent number 10,546,929
- Issue date Jan 28, 2020
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- François Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit comprising balanced cells at the active
- Patent number 10,504,897
- Issue date Dec 10, 2019
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit including balanced cells limiting an active area
- Patent number 10,446,548
- Issue date Oct 15, 2019
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit chip with strained NMOS and PMOS transistors
- Patent number 10,418,486
- Issue date Sep 17, 2019
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming strained MOS transistors
- Patent number 10,263,110
- Issue date Apr 16, 2019
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with NMOS and PMOS transistors having different...
- Patent number 9,985,029
- Issue date May 29, 2018
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a device with MOS transistors
- Patent number 9,876,032
- Issue date Jan 23, 2018
- STMicroelectronics (Crolles 2) SAS
- Sonarith Chhun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a substrate provided with different active...
- Patent number 9,558,957
- Issue date Jan 31, 2017
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit comprising PMOS transistors with different volta...
- Patent number 9,520,330
- Issue date Dec 13, 2016
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating SOI transistors for an increased integratio...
- Patent number 9,514,996
- Issue date Dec 6, 2016
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a semiconductor structure with a buried ground plane
- Patent number 9,214,515
- Issue date Dec 15, 2015
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Yannick Le Tiec
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a transistor comprising nanoscale semicondu...
- Patent number 9,147,750
- Issue date Sep 29, 2015
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Simeon Morvan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for stressing a thin pattern and transistor fabrication meth...
- Patent number 8,853,023
- Issue date Oct 7, 2014
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Simeon Morvan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of adjusting the threshold voltage of a transistor by a buri...
- Patent number 8,809,964
- Issue date Aug 19, 2014
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- François Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a semiconductor structure with a buried ground plane
- Patent number 8,501,588
- Issue date Aug 6, 2013
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Yannick Le Tiec
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of active areas of different natures directly onto an i...
- Patent number 7,820,523
- Issue date Oct 26, 2010
- Commissariat a l'Energie Atomique
- François Andrieu
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL NOR MEMORY STRUCTURE
- Publication number 20240153566
- Publication date May 9, 2024
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Mona EZZADEEN
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE FOR DRIVING TRANSISTORS AND METHOD OF DRIVING
- Publication number 20230413581
- Publication date Dec 21, 2023
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Bastien GIRAUD
- G11 - INFORMATION STORAGE
Information Patent Application
NEUROMORPHIC CIRCUIT BASED ON 2T2R RRAM CELLS
- Publication number 20230059091
- Publication date Feb 23, 2023
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Mona EZZADEEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
1T1R MEMORY WITH A 3D STRUCTURE
- Publication number 20220415967
- Publication date Dec 29, 2022
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Sylvain BARRAUD
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR FORMING A USEFUL SUBSTRATE TRAPPING STRUCTURE
- Publication number 20220148908
- Publication date May 12, 2022
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Emmanuel Augendre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A MICROELECTRONIC DEVICE
- Publication number 20220028728
- Publication date Jan 27, 2022
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Heimanu NIEBOJEWSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE COMPRISING WRAP-GATE TRANSISTORS AND METHOD OF MANUFACTURING...
- Publication number 20210296398
- Publication date Sep 23, 2021
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Sylvain BARRAUD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D MEMORY AND MANUFACTURING PROCESS
- Publication number 20210193738
- Publication date Jun 24, 2021
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Sylvain BARRAUD
- G11 - INFORMATION STORAGE
Information Patent Application
IMAGE SENSOR FORMED IN SEQUENTIAL 3D TECHNOLOGY
- Publication number 20210082983
- Publication date Mar 18, 2021
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Lina Kadura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RESISTIVE 3D MEMORY
- Publication number 20210028231
- Publication date Jan 28, 2021
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- François ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D CIRCUIT PROVIDED WITH MESA ISOLATION FOR THE GROUND PLANE ZONE
- Publication number 20200203229
- Publication date Jun 25, 2020
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Perrine BATUDE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A SEMICONDUCTOR SUBSTRATE HAVING A STRESSED S...
- Publication number 20200194273
- Publication date Jun 18, 2020
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Shay REBOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRODUCTION OF A 3D CIRCUIT WITH UPPER LEVEL TRANSISTOR PROVIDED WIT...
- Publication number 20200035561
- Publication date Jan 30, 2020
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Perrine BATUDE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT CHIP WITH STRAINED NMOS AND PMOS TRANSISTORS
- Publication number 20190363190
- Publication date Nov 28, 2019
- STMicroelectronics (Crolles 2) SAS
- Remy BERTHELON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D SRAM CIRCUIT WITH DOUBLE GATE TRANSISTORS WITH IMPROVED LAYOUT
- Publication number 20190312039
- Publication date Oct 10, 2019
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASSEMBLY FOR 3D CIRCUIT WITH SUPERPOSED TRANSISTOR LEVELS
- Publication number 20190198397
- Publication date Jun 27, 2019
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Francois ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D CIRCUIT TRANSISTORS WITH FLIPPED GATE
- Publication number 20190157300
- Publication date May 23, 2019
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Francois ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTORS DOUBLE GRILLES OPTIMISES ET PROCEDE DE FABRICATION
- Publication number 20190027560
- Publication date Jan 24, 2019
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- François ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT CHIP WITH STRAINED NMOS AND PMOS TRANSISTORS
- Publication number 20180331221
- Publication date Nov 15, 2018
- STMicroelectronics (Crolles 2) SAS
- Remy BERTHELON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT INCLUDING BALANCED CELLS LIMITING AN ACTIVE AREA
- Publication number 20180083005
- Publication date Mar 22, 2018
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Francois ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT INCLUDING BALANCED CELLS LIMITING AN ACTIVE AREA
- Publication number 20180083006
- Publication date Mar 22, 2018
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Francois ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT COMPRISING TRANSISTORS HAVING DIFFERENT THRESHOL...
- Publication number 20180026036
- Publication date Jan 25, 2018
- Commissariat a I'Energie Atomique et aux Energies Alternatives
- Francois ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING STRAINED MOS TRANSISTORS
- Publication number 20170194498
- Publication date Jul 6, 2017
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING A DEVICE WITH MOS TRANSISTORS
- Publication number 20170117296
- Publication date Apr 27, 2017
- STMicroelectronics (Crolles 2) SAS
- Sonarith Chhun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR FABRICATING SOI TRANSISTORS FOR AN INCREASED INTEGRATIO...
- Publication number 20160307809
- Publication date Oct 20, 2016
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Francois ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH DIFFERENT VOLTA...
- Publication number 20160197018
- Publication date Jul 7, 2016
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Francois ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR RELAXING THE TRANSVERSE MECHANICAL STRESSES WITHIN THE A...
- Publication number 20160099183
- Publication date Apr 7, 2016
- STMicroelectronics (Crolles 2) SAS
- Denis Rideau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR RELAXING THE TRANSVERSE MECHANICAL STRESSES WITHIN THE A...
- Publication number 20150097241
- Publication date Apr 9, 2015
- STMicroelectronics (Crolles 2) SAS
- Denis Rideau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE WITH A BURIED GROUND PLANE
- Publication number 20130341649
- Publication date Dec 26, 2013
- Yannick Le Tiec
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR FABRICATING A TRANSISTOR COMPRISING NANOSCALE SEMICONDU...
- Publication number 20130323888
- Publication date Dec 5, 2013
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Simeon MORVAN
- H01 - BASIC ELECTRIC ELEMENTS

Francois Andrieu

Person

Patents Grantslast 30 patents

Device comprising wrap-gate transistors and method of manufacturing...

Image sensor formed in sequential 3D technology

Method of fabricating a semiconductor substrate having a stressed s...

Resistive 3D memory

Method for manufacturing a microelectronic device

3D memory and manufacturing process

3D circuit provided with mesa isolation for the ground plane zone

Assembly for 3D circuit with superposed transistor levels

Production of a 3D circuit with upper level transistor provided wit...

Integrated circuit chip with strained NMOS and PMOS transistors

3D SRAM circuit with double gate transistors with improved layout

3D circuit transistors with flipped gate

Optimized double-gate transistors and fabricating process

Integrated circuit comprising balanced cells at the active

Integrated circuit including balanced cells limiting an active area

Integrated circuit chip with strained NMOS and PMOS transistors

Method of forming strained MOS transistors

Integrated circuit with NMOS and PMOS transistors having different...

Method of manufacturing a device with MOS transistors

Method for manufacturing a substrate provided with different active...

Integrated circuit comprising PMOS transistors with different volta...

Process for fabricating SOI transistors for an increased integratio...

Method for making a semiconductor structure with a buried ground plane

Process for fabricating a transistor comprising nanoscale semicondu...

Method for stressing a thin pattern and transistor fabrication meth...

Method of adjusting the threshold voltage of a transistor by a buri...

Method for making a semiconductor structure with a buried ground plane

Fabrication of active areas of different natures directly onto an i...

Patents Applicationslast 30 patents

THREE-DIMENSIONAL NOR MEMORY STRUCTURE

DEVICE FOR DRIVING TRANSISTORS AND METHOD OF DRIVING

NEUROMORPHIC CIRCUIT BASED ON 2T2R RRAM CELLS

1T1R MEMORY WITH A 3D STRUCTURE

METHOD FOR FORMING A USEFUL SUBSTRATE TRAPPING STRUCTURE

METHOD FOR MANUFACTURING A MICROELECTRONIC DEVICE

DEVICE COMPRISING WRAP-GATE TRANSISTORS AND METHOD OF MANUFACTURING...

3D MEMORY AND MANUFACTURING PROCESS

IMAGE SENSOR FORMED IN SEQUENTIAL 3D TECHNOLOGY

RESISTIVE 3D MEMORY

3D CIRCUIT PROVIDED WITH MESA ISOLATION FOR THE GROUND PLANE ZONE

METHOD OF FABRICATING A SEMICONDUCTOR SUBSTRATE HAVING A STRESSED S...

PRODUCTION OF A 3D CIRCUIT WITH UPPER LEVEL TRANSISTOR PROVIDED WIT...

INTEGRATED CIRCUIT CHIP WITH STRAINED NMOS AND PMOS TRANSISTORS

3D SRAM CIRCUIT WITH DOUBLE GATE TRANSISTORS WITH IMPROVED LAYOUT

ASSEMBLY FOR 3D CIRCUIT WITH SUPERPOSED TRANSISTOR LEVELS

3D CIRCUIT TRANSISTORS WITH FLIPPED GATE

TRANSISTORS DOUBLE GRILLES OPTIMISES ET PROCEDE DE FABRICATION

INTEGRATED CIRCUIT CHIP WITH STRAINED NMOS AND PMOS TRANSISTORS

INTEGRATED CIRCUIT INCLUDING BALANCED CELLS LIMITING AN ACTIVE AREA

INTEGRATED CIRCUIT INCLUDING BALANCED CELLS LIMITING AN ACTIVE AREA

INTEGRATED CIRCUIT COMPRISING TRANSISTORS HAVING DIFFERENT THRESHOL...

METHOD OF FORMING STRAINED MOS TRANSISTORS

METHOD OF MANUFACTURING A DEVICE WITH MOS TRANSISTORS

PROCESS FOR FABRICATING SOI TRANSISTORS FOR AN INCREASED INTEGRATIO...

INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH DIFFERENT VOLTA...

METHOD FOR RELAXING THE TRANSVERSE MECHANICAL STRESSES WITHIN THE A...

METHOD FOR RELAXING THE TRANSVERSE MECHANICAL STRESSES WITHIN THE A...

METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE WITH A BURIED GROUND PLANE

PROCESS FOR FABRICATING A TRANSISTOR COMPRISING NANOSCALE SEMICONDU...