Frank Koschinsky

Person

Radebeul, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Method including a formation of a diffusion barrier and semiconduct...
- Patent number 10,090,195
- Issue date Oct 2, 2018
- GLOBALFOUNDRIES Inc.
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming metal nitride materials
- Patent number 9,177,826
- Issue date Nov 3, 2015
- GLOBALFOUNDRIES Inc.
- Bernd Hintze
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating integrated circuits including barrier layer...
- Patent number 9,177,858
- Issue date Nov 3, 2015
- GLOBALFOUNDRIES, INC.
- Xunyuan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method including an etching of a portion of an interlayer dielectri...
- Patent number 9,171,754
- Issue date Oct 27, 2015
- GLOBALFOUNDRIES Inc.
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for detecting defects in a diffusion barrier layer
- Patent number 9,147,618
- Issue date Sep 29, 2015
- GLOBALFOUNDRIES Inc.
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-step deposition control
- Patent number 8,585,877
- Issue date Nov 19, 2013
- Advanced Micro Devices, Inc.
- Roland Jaeger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test system and method of reducing damage in seed layers in metalli...
- Patent number 8,323,989
- Issue date Dec 4, 2012
- GLOBALFOUNDRIES, INC.
- Frank Feustel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-step deposition control
- Patent number 8,163,571
- Issue date Apr 24, 2012
- Advanced Micro Devices, Inc.
- Roland Jaeger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of testing an integrity of a material layer in a semiconduct...
- Patent number 8,058,081
- Issue date Nov 15, 2011
- Advanced Micro Devices, Inc.
- Moritz Andreas Meyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced wafer warpage in semiconductors by stress engineering in th...
- Patent number 8,053,354
- Issue date Nov 8, 2011
- GLOBALFOUNDRIES Inc.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing contamination of semiconductor substrates during BEOL proc...
- Patent number 8,039,400
- Issue date Oct 18, 2011
- GLOBALFOUNDRIES Inc.
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for removing a passivation layer prior to depositing a barri...
- Patent number 7,820,536
- Issue date Oct 26, 2010
- Advanced Micro Devices, Inc.
- Holger Schuehrer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for cleaning the surface of a substrate
- Patent number 7,063,091
- Issue date Jun 20, 2006
- Advanced Micro Devices, Inc.
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Void formation monitoring in a damascene process
- Patent number 6,964,874
- Issue date Nov 15, 2005
- Advanced Micro Devices, Inc.
- Thomas Werner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interface void monitoring in a damascene process
- Patent number 6,716,650
- Issue date Apr 6, 2004
- Advanced Micro Devices, Inc.
- Eckhard Langer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metallization process sequence for a barrier metal layer
- Patent number 6,613,660
- Issue date Sep 2, 2003
- Advanced Micro Devices, Inc.
- Volker Kahlert
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD INCLUDING A FORMATION OF A DIFFUSION BARRIER AND SEMICONDUCT...
- Publication number 20170117179
- Publication date Apr 27, 2017
- GLOBALFOUNDRIES INC.
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BARRIER LAYER...
- Publication number 20150325467
- Publication date Nov 12, 2015
- GLOBALFOUNDRIES, Inc.
- Xunyuan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR DETECTING DEFECTS IN A DIFFUSION BARRIER LAYER
- Publication number 20150111316
- Publication date Apr 23, 2015
- GLOBALFOUNDRIES INC.
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD INCLUDING AN ETCHING OF A PORTION OF AN INTERLAYER DIELECTRI...
- Publication number 20140349478
- Publication date Nov 27, 2014
- GLOBALFOUNDRIES INC.
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING BARRIER LAYERS FOR CONDUCTIVE COPPER STRUCTURES
- Publication number 20140273436
- Publication date Sep 18, 2014
- GLOBALFOUNDRIES INC.
- Bernd Hintze
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESSES FOR FORMING INTEGRATED CIRCUITS WITH POST-PATTERNING TREA...
- Publication number 20140024213
- Publication date Jan 23, 2014
- GLOBALFOUNDRIES INC.
- Bernd Hintze
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of Forming Metal Nitride Materials
- Publication number 20130203266
- Publication date Aug 8, 2013
- GLOBALFOUNDRIES INC.
- Bernd Hintze
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-STEP DEPOSITION CONTROL
- Publication number 20120160415
- Publication date Jun 28, 2012
- Advanced Micro Devices, Inc.
- Roland JAEGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLI...
- Publication number 20100244028
- Publication date Sep 30, 2010
- Frank Feustel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED WAFER WARPAGE IN SEMICONDUCTORS BY STRESS ENGINEERING IN TH...
- Publication number 20100109131
- Publication date May 6, 2010
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROC...
- Publication number 20090325378
- Publication date Dec 31, 2009
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-STEP DEPOSITION CONTROL
- Publication number 20080299681
- Publication date Dec 4, 2008
- Roland Jaeger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF TESTING AN INTEGRITY OF A MATERIAL LAYER IN A SEMICONDUCT...
- Publication number 20080160654
- Publication date Jul 3, 2008
- Moritz Andreas Meyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REMOVING A PASSIVATION LAYER PRIOR TO DEPOSITING A BARRI...
- Publication number 20070123034
- Publication date May 31, 2007
- Holger Schuehrer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE COMPRISING COPPER-BASED CONTACT PLUG AND A MET...
- Publication number 20070096221
- Publication date May 3, 2007
- Kai Frohberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUE FOR FORMING A COPPER-BASED METALLIZATION LAYER INCLUDING...
- Publication number 20070077761
- Publication date Apr 5, 2007
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming electrically conductive lines in an integrated ci...
- Publication number 20060267207
- Publication date Nov 30, 2006
- Frank Feustel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Technique for forming copper-containing lines embedded in a low-k d...
- Publication number 20060267201
- Publication date Nov 30, 2006
- Peter Huebler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for cleaning the surface of a substrate
- Publication number 20050230344
- Publication date Oct 20, 2005
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Void formation monitoring in a damascene process
- Publication number 20030082901
- Publication date May 1, 2003
- Thomas Werner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metallization process sequence
- Publication number 20030054625
- Publication date Mar 20, 2003
- Volker Kahlert
- H01 - BASIC ELECTRIC ELEMENTS

Frank Koschinsky

Person

Patents Grantslast 30 patents

Method including a formation of a diffusion barrier and semiconduct...

Methods of forming metal nitride materials

Methods for fabricating integrated circuits including barrier layer...

Method including an etching of a portion of an interlayer dielectri...

Method for detecting defects in a diffusion barrier layer

Multi-step deposition control

Test system and method of reducing damage in seed layers in metalli...

Multi-step deposition control

Method of testing an integrity of a material layer in a semiconduct...

Reduced wafer warpage in semiconductors by stress engineering in th...

Reducing contamination of semiconductor substrates during BEOL proc...

Method for removing a passivation layer prior to depositing a barri...

Method for cleaning the surface of a substrate

Void formation monitoring in a damascene process

Interface void monitoring in a damascene process

Metallization process sequence for a barrier metal layer

Patents Applicationslast 30 patents

METHOD INCLUDING A FORMATION OF A DIFFUSION BARRIER AND SEMICONDUCT...

METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BARRIER LAYER...

METHOD FOR DETECTING DEFECTS IN A DIFFUSION BARRIER LAYER

METHOD INCLUDING AN ETCHING OF A PORTION OF AN INTERLAYER DIELECTRI...

METHODS OF FORMING BARRIER LAYERS FOR CONDUCTIVE COPPER STRUCTURES

PROCESSES FOR FORMING INTEGRATED CIRCUITS WITH POST-PATTERNING TREA...

Methods of Forming Metal Nitride Materials

MULTI-STEP DEPOSITION CONTROL

TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLI...

REDUCED WAFER WARPAGE IN SEMICONDUCTORS BY STRESS ENGINEERING IN TH...

REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROC...

MULTI-STEP DEPOSITION CONTROL

METHOD OF TESTING AN INTEGRITY OF A MATERIAL LAYER IN A SEMICONDUCT...

METHOD FOR REMOVING A PASSIVATION LAYER PRIOR TO DEPOSITING A BARRI...

SEMICONDUCTOR DEVICE COMPRISING COPPER-BASED CONTACT PLUG AND A MET...

TECHNIQUE FOR FORMING A COPPER-BASED METALLIZATION LAYER INCLUDING...

Method of forming electrically conductive lines in an integrated ci...

Technique for forming copper-containing lines embedded in a low-k d...

Method for cleaning the surface of a substrate

Void formation monitoring in a damascene process

Metallization process sequence