Frank T. Hady

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Coherent multiprocessing enabled compute in storage and memory
- Patent number 12,061,550
- Issue date Aug 13, 2024
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load reduced nonvolatile memory interface
- Patent number 11,789,880
- Issue date Oct 17, 2023
- SK hynix NAND Product Solutions Corp.
- Emily P. Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load reduced nonvolatile memory interface
- Patent number 11,500,795
- Issue date Nov 15, 2022
- Intel Corporation
- Emily P. Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Caching for heterogeneous processors
- Patent number 11,016,895
- Issue date May 25, 2021
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level memory with direct access
- Patent number 10,817,201
- Issue date Oct 27, 2020
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load reduced nonvolatile memory interface
- Patent number 10,459,855
- Issue date Oct 29, 2019
- Intel Corporation
- Emily Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Caching for heterogeneous processors
- Patent number 10,339,061
- Issue date Jul 2, 2019
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to provide both storage mode and memory mode a...
- Patent number 10,318,185
- Issue date Jun 11, 2019
- Intel Corporation
- Frank Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level memory with direct access
- Patent number 10,241,710
- Issue date Mar 26, 2019
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing disturbance induced errors
- Patent number 10,153,015
- Issue date Dec 11, 2018
- Intel Corporation
- Prashant S. Damle
- G11 - INFORMATION STORAGE
Information Patent Grant
Interchangeable power and signal contacts for IO connectors
- Patent number 10,089,270
- Issue date Oct 2, 2018
- Intel Corporation
- Stephen R. Mooney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for processing sequential writes to a block gr...
- Patent number 10,031,845
- Issue date Jul 24, 2018
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for processing sequential writes to portions o...
- Patent number 10,019,198
- Issue date Jul 10, 2018
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Caching for heterogeneous processors
- Patent number 9,965,393
- Issue date May 8, 2018
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host controlled IO power management
- Patent number 9,804,646
- Issue date Oct 31, 2017
- Intel Corporation
- James E. Jaussi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing disturbance induced errors
- Patent number 9,792,963
- Issue date Oct 17, 2017
- Intel Corporation
- Prashant S. Damle
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level memory with direct access
- Patent number 9,703,502
- Issue date Jul 11, 2017
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level memory with direct access
- Patent number 9,430,151
- Issue date Aug 30, 2016
- Intel Corporation
- Blaise Fanning
- G11 - INFORMATION STORAGE
Information Patent Grant
Universal IO connector and interface capable of both wired and wire...
- Patent number 9,312,908
- Issue date Apr 12, 2016
- Intel Corporation
- Stephen R. Mooney
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Caching for heterogeneous processors
- Patent number 9,235,550
- Issue date Jan 12, 2016
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing disturbance induced errors
- Patent number 9,202,547
- Issue date Dec 1, 2015
- Intel Corporation
- Prashant S. Damle
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level memory with direct access
- Patent number 9,190,124
- Issue date Nov 17, 2015
- Intel Corporation
- Blaise Fanning
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method to accelerate access to network data using a netw...
- Patent number 9,152,432
- Issue date Oct 6, 2015
- Intel Corporation
- Mason Cabot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronizing multiple system clocks
- Patent number 8,934,505
- Issue date Jan 13, 2015
- Intel Corporation
- Kevin Stanton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Caching for heterogeneous processors
- Patent number 8,799,579
- Issue date Aug 5, 2014
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling peripheral communication in a local area network
- Patent number 8,719,454
- Issue date May 6, 2014
- Intel Corporation
- Frank Hady
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Caching for heterogeneous processors
- Patent number 8,402,222
- Issue date Mar 19, 2013
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system to perform caching based on file-level heuristics
- Patent number 8,171,219
- Issue date May 1, 2012
- Intel Corporation
- Sanjeev N. Trika
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous processors sharing a common cache
- Patent number 8,156,285
- Issue date Apr 10, 2012
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggregation of file/directory structures
- Patent number 8,140,474
- Issue date Mar 20, 2012
- Intel Corporation
- Frank Hady
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COHERENT MULTIPROCESSING ENABLED COMPUTE IN STORAGE AND MEMORY
- Publication number 20240378150
- Publication date Nov 14, 2024
- Intel Corporation
- Frank T. HADY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD REDUCED NONVOLATILE MEMORY INTERFACE
- Publication number 20230116774
- Publication date Apr 13, 2023
- SK Hynix NAND Product Solutions Corp. (dba Solidigm)
- Emily P. Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COHERENT MULTIPROCESSING ENABLED COMPUTE IN STORAGE AND MEMORY
- Publication number 20200226067
- Publication date Jul 16, 2020
- Intel Corporation
- Frank T. HADY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD REDUCED NONVOLATILE MEMORY INTERFACE
- Publication number 20200133899
- Publication date Apr 30, 2020
- Intel Corporation
- Emily P. CHUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL MEMORY WITH DIRECT ACCESS
- Publication number 20190286356
- Publication date Sep 19, 2019
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHING FOR HETEROGENEOUS PROCESSORS
- Publication number 20190114261
- Publication date Apr 18, 2019
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Input/Output Access to Memory or Storage by a Virtua...
- Publication number 20180088978
- Publication date Mar 29, 2018
- Intel Corporation
- Yadong Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING DISTURBANCE INDUCED ERRORS
- Publication number 20180068695
- Publication date Mar 8, 2018
- Intel Corporation
- Prashant S. DAMLE
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS TO PROVIDE BOTH STORAGE MODE AND MEMORY MODE A...
- Publication number 20180004438
- Publication date Jan 4, 2018
- Intel Corporation
- Frank Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD REDUCED NONVOLATILE MEMORY INTERFACE
- Publication number 20180004688
- Publication date Jan 4, 2018
- Intel Corporation
- Emily CHUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL MEMORY WITH DIRECT ACCESS
- Publication number 20170337009
- Publication date Nov 23, 2017
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PROCESSING SEQUENTIAL WRITES TO A BLOCK GR...
- Publication number 20170286287
- Publication date Oct 5, 2017
- Intel Corporation
- Frank T. HADY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PROCESSING SEQUENTIAL WRITES TO PORTIONS O...
- Publication number 20170286014
- Publication date Oct 5, 2017
- Intel Corporation
- Frank T. HADY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHING FOR HETEROGENEOUS PROCESSORS
- Publication number 20170097888
- Publication date Apr 6, 2017
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHING FOR HETEROGENEOUS PROCESSORS
- Publication number 20170097889
- Publication date Apr 6, 2017
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL MEMORY WITH DIRECT ACCESS
- Publication number 20170075616
- Publication date Mar 16, 2017
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHING FOR HETEROGENEOUS PROCESSORS
- Publication number 20160188466
- Publication date Jun 30, 2016
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING DISTURBANCE INDUCED ERRORS
- Publication number 20160189757
- Publication date Jun 30, 2016
- PRASHANT S. DAMLE
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-LEVEL MEMORY WITH DIRECT ACCESS
- Publication number 20160110106
- Publication date Apr 21, 2016
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHING FOR HETEROGENEOUS PROCESSORS
- Publication number 20150081976
- Publication date Mar 19, 2015
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH...
- Publication number 20140317337
- Publication date Oct 23, 2014
- Leena K. Puthiyedath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING DISTURBANCE INDUCED ERRORS
- Publication number 20140281203
- Publication date Sep 18, 2014
- PRASHANT S. DAMLE
- G11 - INFORMATION STORAGE
Information Patent Application
UNIVERSAL IO CONNECTOR AND INTERFACE CAPABLE OF BOTH WIRED AND WIRE...
- Publication number 20140242927
- Publication date Aug 28, 2014
- Stephen R. Mooney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCHANGEABLE POWER AND SIGNAL CONTACTS FOR IO CONNECTORS
- Publication number 20140197696
- Publication date Jul 17, 2014
- Stephen R. Mooney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL MEMORY WITH DIRECT ACCESS
- Publication number 20130339572
- Publication date Dec 19, 2013
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST CONTROLLED IO POWER MANAGEMENT
- Publication number 20130283070
- Publication date Oct 24, 2013
- James E. Jaussi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHING FOR HETEROGENEOUS PROCESSORS
- Publication number 20130275681
- Publication date Oct 17, 2013
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS PROCESSORS SHARING A COMMON CACHE
- Publication number 20120215984
- Publication date Aug 23, 2012
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONIZING MULTIPLE SYSTEM CLOCKS
- Publication number 20120170597
- Publication date Jul 5, 2012
- Kevin Stanton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND SYSTEM TO PERFORM CACHING BASED ON FILE-LEVEL HEURISTICS
- Publication number 20100250834
- Publication date Sep 30, 2010
- Sanjeev N. Trika
- G06 - COMPUTING CALCULATING COUNTING

Frank T. Hady

Person

Patents Grantslast 30 patents

Coherent multiprocessing enabled compute in storage and memory

Load reduced nonvolatile memory interface

Load reduced nonvolatile memory interface

Caching for heterogeneous processors

Multi-level memory with direct access

Load reduced nonvolatile memory interface

Caching for heterogeneous processors

Method and apparatus to provide both storage mode and memory mode a...

Multi-level memory with direct access

Managing disturbance induced errors

Interchangeable power and signal contacts for IO connectors

Method and apparatus for processing sequential writes to a block gr...

Method and apparatus for processing sequential writes to portions o...

Caching for heterogeneous processors

Host controlled IO power management

Managing disturbance induced errors

Multi-level memory with direct access

Multi-level memory with direct access

Universal IO connector and interface capable of both wired and wire...

Caching for heterogeneous processors

Managing disturbance induced errors

Multi-level memory with direct access

System and method to accelerate access to network data using a netw...

Synchronizing multiple system clocks

Caching for heterogeneous processors

Enabling peripheral communication in a local area network

Caching for heterogeneous processors

Method and system to perform caching based on file-level heuristics

Heterogeneous processors sharing a common cache

Aggregation of file/directory structures

Patents Applicationslast 30 patents

COHERENT MULTIPROCESSING ENABLED COMPUTE IN STORAGE AND MEMORY

LOAD REDUCED NONVOLATILE MEMORY INTERFACE

COHERENT MULTIPROCESSING ENABLED COMPUTE IN STORAGE AND MEMORY

LOAD REDUCED NONVOLATILE MEMORY INTERFACE

MULTI-LEVEL MEMORY WITH DIRECT ACCESS

CACHING FOR HETEROGENEOUS PROCESSORS

Techniques for Input/Output Access to Memory or Storage by a Virtua...

MANAGING DISTURBANCE INDUCED ERRORS

METHOD AND APPARATUS TO PROVIDE BOTH STORAGE MODE AND MEMORY MODE A...

LOAD REDUCED NONVOLATILE MEMORY INTERFACE

MULTI-LEVEL MEMORY WITH DIRECT ACCESS

METHOD AND APPARATUS FOR PROCESSING SEQUENTIAL WRITES TO A BLOCK GR...

METHOD AND APPARATUS FOR PROCESSING SEQUENTIAL WRITES TO PORTIONS O...

CACHING FOR HETEROGENEOUS PROCESSORS

CACHING FOR HETEROGENEOUS PROCESSORS

MULTI-LEVEL MEMORY WITH DIRECT ACCESS

CACHING FOR HETEROGENEOUS PROCESSORS

MANAGING DISTURBANCE INDUCED ERRORS

MULTI-LEVEL MEMORY WITH DIRECT ACCESS

CACHING FOR HETEROGENEOUS PROCESSORS

METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH...

MANAGING DISTURBANCE INDUCED ERRORS

UNIVERSAL IO CONNECTOR AND INTERFACE CAPABLE OF BOTH WIRED AND WIRE...

INTERCHANGEABLE POWER AND SIGNAL CONTACTS FOR IO CONNECTORS

MULTI-LEVEL MEMORY WITH DIRECT ACCESS

HOST CONTROLLED IO POWER MANAGEMENT

CACHING FOR HETEROGENEOUS PROCESSORS

HETEROGENEOUS PROCESSORS SHARING A COMMON CACHE

SYNCHRONIZING MULTIPLE SYSTEM CLOCKS

METHOD AND SYSTEM TO PERFORM CACHING BASED ON FILE-LEVEL HEURISTICS