Franz Neppl

Person

Munich, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Method for detaching chips from a wafer
- Patent number 5,597,766
- Issue date Jan 28, 1997
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit containing bi-polar and complementary MOS transi...
- Patent number 5,100,811
- Issue date Mar 31, 1992
- Siemens Aktiengesellschaft
- Josef Winnerl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit containing integrated bipolar and complementary MOS transis...
- Patent number 5,034,338
- Issue date Jul 23, 1991
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making an integrated circuit comprising load resistors ar...
- Patent number 5,013,678
- Issue date May 7, 1991
- Siemens Aktiengesellschaft
- Josef Winnerl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for self-aligned manufacture of contacts between interconnec...
- Patent number 4,960,489
- Issue date Oct 2, 1990
- Siemens Aktiengesellschaft
- Guenther Roeska
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated semiconductor circuit having an external contacting trac...
- Patent number 4,912,543
- Issue date Mar 27, 1990
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing wells for CMOS transistor circuits separat...
- Patent number 4,906,585
- Issue date Mar 6, 1990
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal-oxide semiconductor (MOS) field effect transistor having extr...
- Patent number 4,885,617
- Issue date Dec 5, 1989
- Siemens Aktiengesellschaft
- C. A. Mazure-Espejo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit containing integrated bipolar and complementary MOS transis...
- Patent number 4,884,117
- Issue date Nov 28, 1989
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor circuit containing integrated bipolar and MOS transis...
- Patent number 4,874,717
- Issue date Oct 17, 1989
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing integrated circuit containing bipolar and c...
- Patent number 4,855,245
- Issue date Aug 8, 1989
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for making neighboring wells for VLS1 CMOS components
- Patent number 4,803,179
- Issue date Feb 7, 1989
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for producing CMOS having doped polysilicon gate by outdiff...
- Patent number 4,782,033
- Issue date Nov 1, 1988
- Siemens Aktiengesellschaft
- Heike Gierisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming retrograde twin wells by outdiffusion of impurity ions in e...
- Patent number 4,761,384
- Issue date Aug 2, 1988
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for the manufacture of cross-couplings between n-channel and...
- Patent number 4,740,479
- Issue date Apr 26, 1988
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated semiconductor circuit including a tantalum silicide diff...
- Patent number 4,680,612
- Issue date Jul 14, 1987
- Siemens Aktiengesellschaft
- Konrad Hieber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated MOS transistors having a gate metallization composed of...
- Patent number 4,673,968
- Issue date Jun 16, 1987
- Siemens Aktiengesellschaft
- Konrad Hieber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for the manufacture of gate electrodes formed of double laye...
- Patent number 4,640,844
- Issue date Feb 3, 1987
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making MOS FETs using silicate glass layer as gate edge m...
- Patent number 4,603,472
- Issue date Aug 5, 1986
- Siemens Aktiengesellschaft
- Ulrich Schwabe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing VLSI complementary MOS field effect circuits
- Patent number 4,525,378
- Issue date Jun 25, 1985
- Siemens Aktiengesellschaft
- Ulrich Schwabe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for the manufacture of integrated MOS-field effect transisto...
- Patent number 4,510,670
- Issue date Apr 16, 1985
- Siemens Aktiengesellschaft
- Ulrich Schwabe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making MOS device using metal silicides or polysilicon fo...
- Patent number 4,505,027
- Issue date Mar 19, 1985
- Siemens Aktiengesellschaft
- Ulrich Schwabe
- H01 - BASIC ELECTRIC ELEMENTS

Franz Neppl

Person

Patents Grantslast 30 patents

Method for detaching chips from a wafer

Integrated circuit containing bi-polar and complementary MOS transi...

Circuit containing integrated bipolar and complementary MOS transis...

Method of making an integrated circuit comprising load resistors ar...

Method for self-aligned manufacture of contacts between interconnec...

Integrated semiconductor circuit having an external contacting trac...

Method for manufacturing wells for CMOS transistor circuits separat...

Metal-oxide semiconductor (MOS) field effect transistor having extr...

Circuit containing integrated bipolar and complementary MOS transis...

Semiconductor circuit containing integrated bipolar and MOS transis...

Method of manufacturing integrated circuit containing bipolar and c...

Methods for making neighboring wells for VLS1 CMOS components

Process for producing CMOS having doped polysilicon gate by outdiff...

Forming retrograde twin wells by outdiffusion of impurity ions in e...

Method for the manufacture of cross-couplings between n-channel and...

Integrated semiconductor circuit including a tantalum silicide diff...

Integrated MOS transistors having a gate metallization composed of...

Method for the manufacture of gate electrodes formed of double laye...

Method of making MOS FETs using silicate glass layer as gate edge m...

Method for manufacturing VLSI complementary MOS field effect circuits

Method for the manufacture of integrated MOS-field effect transisto...

Method of making MOS device using metal silicides or polysilicon fo...