Fred Dunlap

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Strided block transfer instruction
- Patent number 8,432,409
- Issue date Apr 30, 2013
- GlobalFoundries Inc.
- Frederick S. Dunlap
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
System and method for forcing an SRAM into a known state during pow...
- Patent number 7,433,224
- Issue date Oct 7, 2008
- Advanced Micro Devices, Inc.
- Frederick S. Dunlap
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for debugging highly integrated data processors
- Patent number 6,615,368
- Issue date Sep 2, 2003
- National Semiconductor Corporation
- Frederick S. Dunlap
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor architecture for virtualizing selective external bus tran...
- Patent number 6,442,635
- Issue date Aug 27, 2002
- VIA-Cyrix, Inc.
- Thomas B. Brightman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple bus master computer system employing a shared address tran...
- Patent number 5,913,923
- Issue date Jun 22, 1999
- National Semiconductor Corporation
- Frederick S. Dunlap
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor for eliminating external isochronous subsystems
- Patent number 5,838,987
- Issue date Nov 17, 1998
- National Semiconductor Corporation
- Thomas B. Brightman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual display subsystem in a computer
- Patent number 5,786,825
- Issue date Jul 28, 1998
- National Semiconductor
- Bradley W. Cain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor interface supporting I/O or memory mapped communications
- Patent number 5,420,989
- Issue date May 30, 1995
- Cyrix Corporation
- Robert D. Maher
- G06 - COMPUTING CALCULATING COUNTING

Fred Dunlap

Person

Patents Grantslast 30 patents

Strided block transfer instruction

System and method for forcing an SRAM into a known state during pow...

System and method for debugging highly integrated data processors

Processor architecture for virtualizing selective external bus tran...

Multiple bus master computer system employing a shared address tran...

Processor for eliminating external isochronous subsystems

Virtual display subsystem in a computer

Coprocessor interface supporting I/O or memory mapped communications