Frederic C. Amerson

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Peripheral signal handling in extensible three dimensional circuits
- Patent number 8,023,307
- Issue date Sep 20, 2011
- Hewlett-Packard Development Company, L.P.
- Richard J. Carter
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for propagating exception status in data register...
- Patent number 5,778,219
- Issue date Jul 7, 1998
- Hewlett-Packard Company
- Frederic C. Amerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Information processing apparatus with prefetch control for prefetch...
- Patent number 5,721,865
- Issue date Feb 24, 1998
- Hitachi, Ltd.
- Yooichi Shintani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for deferring exceptions generated during specula...
- Patent number 5,692,169
- Issue date Nov 25, 1997
- Hewlett-Packard Company
- Vinod K. Kathail
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector memory operations
- Patent number 5,689,653
- Issue date Nov 18, 1997
- Hewlett-Packard Company
- Alan H. Karp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer architecture for reducing delays due to branch instructions
- Patent number 5,615,386
- Issue date Mar 25, 1997
- Hewlett-Packard Company
- Frederic C. Amerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic allocation of registers to procedures in a digital computer
- Patent number 5,564,031
- Issue date Oct 8, 1996
- Hewlett-Packard Company
- Frederic C. Amerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory processor that prevents errors when load instructions are mo...
- Patent number 5,475,823
- Issue date Dec 12, 1995
- Hewlett-Packard Company
- Frederic C. Amerson
- G06 - COMPUTING CALCULATING COUNTING

Frederic C. Amerson

Person

Patents Grantslast 30 patents

Peripheral signal handling in extensible three dimensional circuits

Method and system for propagating exception status in data register...

Information processing apparatus with prefetch control for prefetch...

Method and system for deferring exceptions generated during specula...

Vector memory operations

Computer architecture for reducing delays due to branch instructions

Dynamic allocation of registers to procedures in a digital computer

Memory processor that prevents errors when load instructions are mo...