Frederic Emirian

Person

Chilly-Mazarin, FR

People

Patents Grantslast 30 patents

Information Patent Grant
FPGA-based hardware emulator system with an inter-FPGA connection s...
- Patent number 11,194,943
- Issue date Dec 7, 2021
- Synopsys, Inc.
- Frédéric Emirian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient power analysis
- Patent number 10,599,794
- Issue date Mar 24, 2020
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a circuit description for a multi-die field-programmable...
- Patent number 9,626,470
- Issue date Apr 18, 2017
- Synopsys, Inc.
- Frederic Emirian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient event detection
- Patent number 9,547,040
- Issue date Jan 17, 2017
- Synopsys, Inc.
- Ludovic Marc Larzul
- G01 - MEASURING TESTING
Information Patent Grant
Generating a circuit description for a multi-die field-programmable...
- Patent number 9,405,878
- Issue date Aug 2, 2016
- Synopsys, Inc.
- Frederic Emirian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a circuit description for a multi-die field-programmable...
- Patent number 9,280,629
- Issue date Mar 8, 2016
- Synopsys, Inc.
- Frederic Emirian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for removing timing hazards in a circuit design
- Patent number 6,301,553
- Issue date Oct 9, 2001
- Luc M. Burgun
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FPGA-BASED HARDWARE EMULATOR SYSTEM WITH AN INTER-FPGA CONNECTION S...
- Publication number 20190179989
- Publication date Jun 13, 2019
- Synopsys, Inc.
- Frédéric Emirian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT EVENT DETECTION
- Publication number 20160327609
- Publication date Nov 10, 2016
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G01 - MEASURING TESTING
Information Patent Application
Generating a Circuit Description for a Multi-Die Field-Programmable...
- Publication number 20160321387
- Publication date Nov 3, 2016
- Synopsys, Inc.
- Frederic Emirian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT POWER ANALYSIS
- Publication number 20160098504
- Publication date Apr 7, 2016
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generating a Circuit Description for a Multi-Die Field-Programmable...
- Publication number 20160048623
- Publication date Feb 18, 2016
- Synopsys, Inc.
- Frederic Emirian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generating a Circuit Description for a Multi-die Field-programmable...
- Publication number 20150135147
- Publication date May 14, 2015
- Synopsys, Inc.
- Frederic Emirian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR EMULATING A DESIGN UNDER TEST ASSOCIATED WITH...
- Publication number 20100161306
- Publication date Jun 24, 2010
- EMULATION AND VERIFICATION ENGINEERING
- Luc Burgun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for emulating a design under test associated with...
- Publication number 20040111252
- Publication date Jun 10, 2004
- EMULATION AND VERIFICATION ENGINEERING
- Luc Burgun
- G06 - COMPUTING CALCULATING COUNTING

Frederic Emirian

Person

Patents Grantslast 30 patents

FPGA-based hardware emulator system with an inter-FPGA connection s...

Efficient power analysis

Generating a circuit description for a multi-die field-programmable...

Efficient event detection

Generating a circuit description for a multi-die field-programmable...

Generating a circuit description for a multi-die field-programmable...

Method and apparatus for removing timing hazards in a circuit design

Patents Applicationslast 30 patents

FPGA-BASED HARDWARE EMULATOR SYSTEM WITH AN INTER-FPGA CONNECTION S...

EFFICIENT EVENT DETECTION

Generating a Circuit Description for a Multi-Die Field-Programmable...

EFFICIENT POWER ANALYSIS

Generating a Circuit Description for a Multi-Die Field-Programmable...

Generating a Circuit Description for a Multi-die Field-programmable...

METHOD AND SYSTEM FOR EMULATING A DESIGN UNDER TEST ASSOCIATED WITH...

Method and system for emulating a design under test associated with...