Frederick R. Dahilig

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and method of forming PIP with inner known goo...
- Patent number RE47923
- Issue date Mar 31, 2020
- STATS ChipPAC Pte. Ltd.
- Zigmund R. Camacho
Information Patent Grant
Semiconductor device and method of forming prefabricated heat sprea...
- Patent number 9,666,540
- Issue date May 30, 2017
- STATS ChipPAC Pte. Ltd.
- Frederick R. Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming prefabricated heat sprea...
- Patent number 9,257,357
- Issue date Feb 9, 2016
- STATS ChipPAC, Ltd.
- Frederick R. Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming wafer level die integration
- Patent number 9,142,514
- Issue date Sep 22, 2015
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with device cavity
- Patent number 8,937,393
- Issue date Jan 20, 2015
- Stats Chippac Ltd.
- Henry Descalzo Bathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming vertical interconnect st...
- Patent number 8,890,328
- Issue date Nov 18, 2014
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming PIP with inner known goo...
- Patent number 8,884,418
- Issue date Nov 11, 2014
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with high lead count and method...
- Patent number 8,810,015
- Issue date Aug 19, 2014
- STAT ChipPAC Ltd.
- Zigmund Ramirez Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming prefabricated heat sprea...
- Patent number 8,518,749
- Issue date Aug 27, 2013
- STATS ChipPAC, Ltd.
- Frederick R. Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor flip chip package having substantially non-collapsibl...
- Patent number 8,405,230
- Issue date Mar 26, 2013
- Stats Chippac Ltd.
- Jae Soo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with interconnect and method of...
- Patent number 8,344,495
- Issue date Jan 1, 2013
- Stats Chippac Ltd.
- Zigmund Ramirez Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming PiP with inner known goo...
- Patent number 8,283,209
- Issue date Oct 9, 2012
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level die integration and method
- Patent number 8,241,954
- Issue date Aug 14, 2012
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system employing device stacking
- Patent number 8,174,127
- Issue date May 8, 2012
- Stats Chippac Ltd.
- Frederick Rodriguez Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system employing device stacking and met...
- Patent number 8,120,187
- Issue date Feb 21, 2012
- Stats Chippac Ltd.
- Frederick Rodriguez Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming vertical interconnect st...
- Patent number 8,105,915
- Issue date Jan 31, 2012
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with increased connectivity and...
- Patent number 8,022,539
- Issue date Sep 20, 2011
- Stats Chippac Ltd.
- Frederick Rodriguez Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor flip chip package having substantially non-collapsibl...
- Patent number 7,880,313
- Issue date Feb 1, 2011
- ChipPAC, Inc.
- Jae Soo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system employing device stacking
- Patent number 7,830,020
- Issue date Nov 9, 2010
- Stats Chippac Ltd.
- Frederick Rodriguez Dahilig
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Device and Method of Forming Prefabricated Heat Sprea...
- Publication number 20160104681
- Publication date Apr 14, 2016
- STATS ChipPAC, Ltd.
- Frederick R. Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOO...
- Publication number 20140284788
- Publication date Sep 25, 2014
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Prefabricated Heat Sprea...
- Publication number 20130256866
- Publication date Oct 3, 2013
- Frederick R. Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming PIP with Inner Known Goo...
- Publication number 20120326302
- Publication date Dec 27, 2012
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Level Die Integration and Method
- Publication number 20120276691
- Publication date Nov 1, 2012
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD O...
- Publication number 20120241968
- Publication date Sep 27, 2012
- Zigmund Ramirez Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Vertical Interconnect St...
- Publication number 20120074567
- Publication date Mar 29, 2012
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND...
- Publication number 20110298113
- Publication date Dec 8, 2011
- Frederick Rodriguez Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING
- Publication number 20110147899
- Publication date Jun 23, 2011
- Frederick Rodriguez Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming PIP with Inner Known Goo...
- Publication number 20110140263
- Publication date Jun 16, 2011
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF...
- Publication number 20110140261
- Publication date Jun 16, 2011
- Zigmund Ramirez Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBL...
- Publication number 20110108970
- Publication date May 12, 2011
- Jae Soo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING AND MET...
- Publication number 20110012270
- Publication date Jan 20, 2011
- Frederick Rodriguez Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF...
- Publication number 20100320591
- Publication date Dec 23, 2010
- Zigmund Ramirez Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Prefabricated Heat Sprea...
- Publication number 20100320588
- Publication date Dec 23, 2010
- STATS ChipPAC, Ltd.
- Frederick R. Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Vertical Interconnect St...
- Publication number 20100314780
- Publication date Dec 16, 2010
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HIGH LEAD COUNT AND METHOD...
- Publication number 20100314731
- Publication date Dec 16, 2010
- Zigmund Ramirez Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD O...
- Publication number 20100123230
- Publication date May 20, 2010
- Frederick Rodriguez Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND...
- Publication number 20100123227
- Publication date May 20, 2010
- Frederick Rodriguez Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Level Die Integration and Method
- Publication number 20090140441
- Publication date Jun 4, 2009
- STATS ChipPAC, Ltd.
- Zigmund R. Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING
- Publication number 20080315411
- Publication date Dec 25, 2008
- Frederick Rodriguez Dahilig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DEVICE CAVITY
- Publication number 20080272479
- Publication date Nov 6, 2008
- Henry Descalzo Bathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor package flip chip interconnect having spacer
- Publication number 20060192295
- Publication date Aug 31, 2006
- ChipPAC, Inc.
- Jae Soo Lee
- H01 - BASIC ELECTRIC ELEMENTS

Frederick R. Dahilig

Person

Patents Grantslast 30 patents

Semiconductor device and method of forming PIP with inner known goo...

Semiconductor device and method of forming prefabricated heat sprea...

Semiconductor device and method of forming prefabricated heat sprea...

Semiconductor device and method of forming wafer level die integration

Integrated circuit package system with device cavity

Semiconductor device and method of forming vertical interconnect st...

Semiconductor device and method of forming PIP with inner known goo...

Integrated circuit packaging system with high lead count and method...

Semiconductor device and method of forming prefabricated heat sprea...

Semiconductor flip chip package having substantially non-collapsibl...

Integrated circuit packaging system with interconnect and method of...

Semiconductor device and method of forming PiP with inner known goo...

Wafer level die integration and method

Integrated circuit package system employing device stacking

Integrated circuit package system employing device stacking and met...

Semiconductor device and method of forming vertical interconnect st...

Integrated circuit packaging system with increased connectivity and...

Semiconductor flip chip package having substantially non-collapsibl...

Integrated circuit package system employing device stacking

Patents Applicationslast 30 patents

Semiconductor Device and Method of Forming Prefabricated Heat Sprea...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOO...

Semiconductor Device and Method of Forming Prefabricated Heat Sprea...

Semiconductor Device and Method of Forming PIP with Inner Known Goo...

Wafer Level Die Integration and Method

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD O...

Semiconductor Device and Method of Forming Vertical Interconnect St...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND...

INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING

Semiconductor Device and Method of Forming PIP with Inner Known Goo...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF...

SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBL...

INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING AND MET...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF...

Semiconductor Device and Method of Forming Prefabricated Heat Sprea...

Semiconductor Device and Method of Forming Vertical Interconnect St...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HIGH LEAD COUNT AND METHOD...

INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD O...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND...

Wafer Level Die Integration and Method

INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DEVICE CAVITY

Semiconductor package flip chip interconnect having spacer