Friedrich Hapke

Person

Winsen/Luhe, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Cell-aware fault model generation for delay faults
- Patent number 8,990,760
- Issue date Mar 24, 2015
- Mentor Graphics Corporation
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Multi-targeting boolean satisfiability-based test pattern generation
- Patent number 8,689,069
- Issue date Apr 1, 2014
- Mentor Graphics Corporation
- Rene Krenz-Baath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed clock control
- Patent number 8,448,008
- Issue date May 21, 2013
- Mentor Graphics Corporation
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
On-chip logic to log failures during production testing and enable...
- Patent number 8,423,845
- Issue date Apr 16, 2013
- Mentor Graphics Corporation
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Testable integrated circuit and test data generation method
- Patent number 8,250,420
- Issue date Aug 21, 2012
- NXP B.V.
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Deterministic logic built-in self-test stimuli generation
- Patent number 8,112,686
- Issue date Feb 7, 2012
- Mentor Graphics Corporation
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
On-chip logic to support compressed X-masking for BIST
- Patent number 8,103,925
- Issue date Jan 24, 2012
- Mentor Graphics Corporation
- Friedrich Hapke
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit arrangement and method of testing an application circuit pr...
- Patent number 7,870,453
- Issue date Jan 11, 2011
- NXP B.V.
- Michael Wittke
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for selectively masking test responses
- Patent number 7,376,873
- Issue date May 20, 2008
- NXP B.V.
- Hendrikus Petrus Elisabeth Vranken
- G01 - MEASURING TESTING
Information Patent Grant
Arrangement and method of testing an integrated circuit
- Patent number 7,143,322
- Issue date Nov 28, 2006
- Koninklijke Philips Electronics N.V.
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with test circuit
- Patent number 7,139,953
- Issue date Nov 21, 2006
- Koninklijke Philips Electronics N.V.
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with self-testing circuit
- Patent number 7,039,844
- Issue date May 2, 2006
- Koninklijke Philips Electronics N.V.
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with self-test circuit
- Patent number 6,789,221
- Issue date Sep 7, 2004
- Koninklijke Philips Electronics N.V.
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Arrangement and method of testing an integrated circuit
- Patent number 6,789,219
- Issue date Sep 7, 2004
- Koninklijke Philips Electronics N.V.
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Arrangement and method having a data word generator for testing int...
- Patent number 6,768,292
- Issue date Jul 27, 2004
- Koninklijke Philips Electronics N.V.
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit for MOS devices
- Patent number 4,398,146
- Issue date Aug 9, 1983
- U.S. Philips Corporation
- Peter Draheim
- G01 - MEASURING TESTING
Information Patent Grant
MOS Integrated test circuit using field effect transistors
- Patent number 4,339,710
- Issue date Jul 13, 1982
- U.S. Philips Corporation
- Friedrich Hapke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit arrangement in MOS-technology with field-effect...
- Patent number 4,336,495
- Issue date Jun 22, 1982
- U.S. Philips Corporation
- Friedrich Hapke
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Cell Internal Defect Diagnosis
- Publication number 20150234978
- Publication date Aug 20, 2015
- Mentor Graphics Corporation
- Huaxing Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TARGETING BOOLEAN SATISFIABILITY-BASED TEST PATTERN GENERATION
- Publication number 20120317454
- Publication date Dec 13, 2012
- Mentor Graphics Corporation
- RENE KRENZ-BAATH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-Chip Logic To Log Failures During Production Testing And Enable...
- Publication number 20110047425
- Publication date Feb 24, 2011
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Application
On-Chip Logic To Support Compressed X-Masking For BIST
- Publication number 20100299567
- Publication date Nov 25, 2010
- Friedrich Hapke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Deterministic Logic Built-In Self-Test Stimuli Generation
- Publication number 20100275075
- Publication date Oct 28, 2010
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Application
On-Chip Logic To Support In-Field Or Post-Tape-Out X-Masking In BIS...
- Publication number 20100253381
- Publication date Oct 7, 2010
- Friedrich Hapke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Speed Clock Control
- Publication number 20100251045
- Publication date Sep 30, 2010
- Mentor Graphics Corporation
- Friedrich HAPKE
- G01 - MEASURING TESTING
Information Patent Application
Cell-Aware Fault Model Creation And Pattern Generation
- Publication number 20100229061
- Publication date Sep 9, 2010
- Friedrich HAPKE
- G01 - MEASURING TESTING
Information Patent Application
TESTABLE INTEGRATED CIRCUIT AND TEST DATA GENERATION METHOD
- Publication number 20100117658
- Publication date May 13, 2010
- NXP, B.V.
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT ARRANGEMENT AND METHOD OF TESTING AND/OR DIAGNOSING THE SAME
- Publication number 20090013230
- Publication date Jan 8, 2009
- NXP B.V.
- Andreas Glowatz
- G01 - MEASURING TESTING
Information Patent Application
Circuit Arrangement and Method of Testing an Application Circuit Pr...
- Publication number 20080195907
- Publication date Aug 14, 2008
- NXP B.V.
- Michael Wittke
- G01 - MEASURING TESTING
Information Patent Application
Method and system for selectively masking test responses
- Publication number 20070067688
- Publication date Mar 22, 2007
- Koninklijke Philips Electronics N.V.
- Hendrikus Petrus Elisabeth Vranken
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit with test circuit
- Publication number 20050160338
- Publication date Jul 21, 2005
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit with self-testing circuit
- Publication number 20050050420
- Publication date Mar 3, 2005
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Application
Arrangement and method for testing integrated circuits
- Publication number 20020144202
- Publication date Oct 3, 2002
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Application
Arrangement and method of testing an integrated circuit
- Publication number 20020069027
- Publication date Jun 6, 2002
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit with self-test circuit
- Publication number 20020069387
- Publication date Jun 6, 2002
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Application
Arrangement and method of testing an integrated circuit
- Publication number 20020069385
- Publication date Jun 6, 2002
- Friedrich Hapke
- G01 - MEASURING TESTING

Friedrich Hapke

Person

Patents Grantslast 30 patents

Cell-aware fault model generation for delay faults

Multi-targeting boolean satisfiability-based test pattern generation

High speed clock control

On-chip logic to log failures during production testing and enable...

Testable integrated circuit and test data generation method

Deterministic logic built-in self-test stimuli generation

On-chip logic to support compressed X-masking for BIST

Circuit arrangement and method of testing an application circuit pr...

Method and system for selectively masking test responses

Arrangement and method of testing an integrated circuit

Integrated circuit with test circuit

Integrated circuit with self-testing circuit

Integrated circuit with self-test circuit

Arrangement and method of testing an integrated circuit

Arrangement and method having a data word generator for testing int...

Test circuit for MOS devices

MOS Integrated test circuit using field effect transistors

Integrated circuit arrangement in MOS-technology with field-effect...

Patents Applicationslast 30 patents

Cell Internal Defect Diagnosis

MULTI-TARGETING BOOLEAN SATISFIABILITY-BASED TEST PATTERN GENERATION

On-Chip Logic To Log Failures During Production Testing And Enable...

On-Chip Logic To Support Compressed X-Masking For BIST

Deterministic Logic Built-In Self-Test Stimuli Generation

On-Chip Logic To Support In-Field Or Post-Tape-Out X-Masking In BIS...

High Speed Clock Control

Cell-Aware Fault Model Creation And Pattern Generation

TESTABLE INTEGRATED CIRCUIT AND TEST DATA GENERATION METHOD

CIRCUIT ARRANGEMENT AND METHOD OF TESTING AND/OR DIAGNOSING THE SAME

Circuit Arrangement and Method of Testing an Application Circuit Pr...

Method and system for selectively masking test responses

Integrated circuit with test circuit

Integrated circuit with self-testing circuit

Arrangement and method for testing integrated circuits

Arrangement and method of testing an integrated circuit

Integrated circuit with self-test circuit

Arrangement and method of testing an integrated circuit