Fu-Chang Hsu

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for NAND flash memory
- Patent number 12,217,808
- Issue date Feb 4, 2025
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for a novel memory array
- Patent number 12,165,717
- Issue date Dec 10, 2024
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for NAND flash memory
- Patent number 12,142,329
- Issue date Nov 12, 2024
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for NAND flash memory
- Patent number 12,100,460
- Issue date Sep 24, 2024
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Quantum bit array
- Patent number 12,029,140
- Issue date Jul 2, 2024
- Fu-Chang Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for NAND flash memory
- Patent number 12,002,525
- Issue date Jun 4, 2024
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for NAND flash memory
- Patent number 11,972,811
- Issue date Apr 30, 2024
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Quantum bit array
- Patent number 11,723,288
- Issue date Aug 8, 2023
- Fu-Chang Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D vertical memory array cell structures with individual selectors...
- Patent number 11,522,016
- Issue date Dec 6, 2022
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for reading NAND flash memory
- Patent number 11,232,835
- Issue date Jan 25, 2022
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional neural network array
- Patent number 11,205,116
- Issue date Dec 21, 2021
- Fu-Chang Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable three-dimensional neural network array
- Patent number 11,182,664
- Issue date Nov 23, 2021
- Fu-Chang Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for NAND flash memory
- Patent number 11,056,190
- Issue date Jul 6, 2021
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for NAND flash memory
- Patent number 11,049,579
- Issue date Jun 29, 2021
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
3D vertical memory array cell structures with individual selectors...
- Patent number 10,840,301
- Issue date Nov 17, 2020
- Fu-Chang Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D vertical memory array cell structures with individual selectors...
- Patent number 10,840,300
- Issue date Nov 17, 2020
- Fu-Chang Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS anti-fuse cell
- Patent number 10,734,088
- Issue date Aug 4, 2020
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for writing nonvolatile 3D NAND flash memory...
- Patent number 10,720,215
- Issue date Jul 21, 2020
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
3D NAND array with divided string architecture
- Patent number 10,553,293
- Issue date Feb 4, 2020
- Fu-Chang Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D vertical memory array cell structures and processes
- Patent number 10,483,324
- Issue date Nov 19, 2019
- Fu-Chang Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS anti-fuse cell
- Patent number 10,395,744
- Issue date Aug 27, 2019
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for writing nonvolatile memory using multiple-...
- Patent number 10,242,743
- Issue date Mar 26, 2019
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for providing multi-page read and write using...
- Patent number 10,199,104
- Issue date Feb 5, 2019
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Compact anti-fuse memory cell using CMOS process
- Patent number 10,163,916
- Issue date Dec 25, 2018
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for storing information using a memory able to...
- Patent number 10,163,509
- Issue date Dec 25, 2018
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS anti-fuse cell
- Patent number 10,109,363
- Issue date Oct 23, 2018
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for providing three-dimensional integrated non...
- Patent number 10,008,265
- Issue date Jun 26, 2018
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
SONOS byte-erasable EEPROM
- Patent number 9,972,392
- Issue date May 15, 2018
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for providing multi-page read and write using...
- Patent number 9,928,911
- Issue date Mar 27, 2018
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS anti-fuse cell
- Patent number 9,793,001
- Issue date Oct 17, 2017
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
3D CELL AND ARRAY STRUCTURES
- Publication number 20240404598
- Publication date Dec 5, 2024
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D CELL AND ARRAY STRUCTURES WITH PARALLEL BIT LINES AND SOURCE LINES
- Publication number 20240306365
- Publication date Sep 12, 2024
- Fu-Chang Hsu
Information Patent Application
3D MEMORY CELLS AND ARRAY ARCHITECTURES
- Publication number 20240284666
- Publication date Aug 22, 2024
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
3D CELL AND ARRAY STRUCTURES
- Publication number 20240274193
- Publication date Aug 15, 2024
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
3D MEMORY CELLS AND ARRAY ARCHITECTURES
- Publication number 20240265969
- Publication date Aug 8, 2024
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
3D CELLS AND ARRAY STRUCTURES AND PROCESSES
- Publication number 20240233821
- Publication date Jul 11, 2024
- Fu-Chang Hsu
Information Patent Application
3D MEMORY CELLS AND ARRAY STRUCTURES
- Publication number 20240233822
- Publication date Jul 11, 2024
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
3D ARRAY STRUCTURES AND PROCESSES
- Publication number 20240233823
- Publication date Jul 11, 2024
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
3D CELLS AND ARRAY STRUCTURES
- Publication number 20240147688
- Publication date May 2, 2024
- Fu-Chang Hsu
Information Patent Application
3D ARRAY STRUCTURES AND PROCESSES
- Publication number 20240135993
- Publication date Apr 25, 2024
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
3D CELLS AND ARRAY STRUCTURES AND PROCESSES
- Publication number 20240138154
- Publication date Apr 25, 2024
- Fu-Chang Hsu
Information Patent Application
3D MEMORY CELLS AND ARRAY STRUCTURES
- Publication number 20240135992
- Publication date Apr 25, 2024
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
Quantum Bit Array
- Publication number 20240130249
- Publication date Apr 18, 2024
- Fu-Chang Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D MEMORY CELLS AND ARRAY ARCHITECTURES AND PROCESSES
- Publication number 20240121938
- Publication date Apr 11, 2024
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
Information Patent Application
3D MEMORY CELLS AND ARRAY ARCHITECTURES
- Publication number 20230397396
- Publication date Dec 7, 2023
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
Information Patent Application
3D MEMORY CELLS AND ARRAY ARCHITECTURES
- Publication number 20230269926
- Publication date Aug 24, 2023
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
Information Patent Application
3D MEMORY CELLS AND ARRAY ARCHITECTURES AND PROCESSES
- Publication number 20230269927
- Publication date Aug 24, 2023
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
Information Patent Application
ADVANCED STRUCTURES HAVING MOSFET TRANSISTORS AND METAL LAYERS
- Publication number 20230154847
- Publication date May 18, 2023
- Fu-Chang Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D MEMORY CELLS AND ARRAY ARCHITECTURES
- Publication number 20230106561
- Publication date Apr 6, 2023
- Fu-Chang Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR NAND FLASH MEMORY
- Publication number 20230022531
- Publication date Jan 26, 2023
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR A NOVEL MEMORY ARRAY
- Publication number 20220351790
- Publication date Nov 3, 2022
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR NEURAL NETWORK ARRAYS
- Publication number 20220164638
- Publication date May 26, 2022
- Fu-Chang Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable Three-Dimensional Neural Network Array
- Publication number 20220083836
- Publication date Mar 17, 2022
- Fu-Chang Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR NAND FLASH MEMORY
- Publication number 20220044746
- Publication date Feb 10, 2022
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSISTOR STRUCTURES AND ASSOCIATED PROCESSES
- Publication number 20220037519
- Publication date Feb 3, 2022
- Fu-Chang Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR NAND FLASH MEMORY
- Publication number 20220028469
- Publication date Jan 27, 2022
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR NAND FLASH MEMORY
- Publication number 20210391027
- Publication date Dec 16, 2021
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR NAND FLASH MEMORY
- Publication number 20210327519
- Publication date Oct 21, 2021
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
THREE DIMENSIONAL DOUBLE-DENSITY MEMORY ARRAY
- Publication number 20210296360
- Publication date Sep 23, 2021
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
QUANTUM BIT ARRAY
- Publication number 20210296556
- Publication date Sep 23, 2021
- Fu-Chang Hsu
- G06 - COMPUTING CALCULATING COUNTING

Fu-Chang Hsu

Person

Patents Grantslast 30 patents

Methods and apparatus for NAND flash memory

Methods and apparatus for a novel memory array

Methods and apparatus for NAND flash memory

Methods and apparatus for NAND flash memory

Quantum bit array

Methods and apparatus for NAND flash memory

Methods and apparatus for NAND flash memory

Quantum bit array

3D vertical memory array cell structures with individual selectors...

Methods and apparatus for reading NAND flash memory

Three-dimensional neural network array

Configurable three-dimensional neural network array

Methods and apparatus for NAND flash memory

Methods and apparatus for NAND flash memory

3D vertical memory array cell structures with individual selectors...

3D vertical memory array cell structures with individual selectors...

CMOS anti-fuse cell

Methods and apparatus for writing nonvolatile 3D NAND flash memory...

3D NAND array with divided string architecture

3D vertical memory array cell structures and processes

CMOS anti-fuse cell

Method and apparatus for writing nonvolatile memory using multiple-...

Method and apparatus for providing multi-page read and write using...

Compact anti-fuse memory cell using CMOS process

Method and apparatus for storing information using a memory able to...

CMOS anti-fuse cell

Method and apparatus for providing three-dimensional integrated non...

SONOS byte-erasable EEPROM

Method and apparatus for providing multi-page read and write using...

CMOS anti-fuse cell

Patents Applicationslast 30 patents

3D CELL AND ARRAY STRUCTURES

3D CELL AND ARRAY STRUCTURES WITH PARALLEL BIT LINES AND SOURCE LINES

3D MEMORY CELLS AND ARRAY ARCHITECTURES

3D CELL AND ARRAY STRUCTURES

3D MEMORY CELLS AND ARRAY ARCHITECTURES

3D CELLS AND ARRAY STRUCTURES AND PROCESSES

3D MEMORY CELLS AND ARRAY STRUCTURES

3D ARRAY STRUCTURES AND PROCESSES

3D CELLS AND ARRAY STRUCTURES

3D ARRAY STRUCTURES AND PROCESSES

3D CELLS AND ARRAY STRUCTURES AND PROCESSES

3D MEMORY CELLS AND ARRAY STRUCTURES

Quantum Bit Array

3D MEMORY CELLS AND ARRAY ARCHITECTURES AND PROCESSES

3D MEMORY CELLS AND ARRAY ARCHITECTURES

3D MEMORY CELLS AND ARRAY ARCHITECTURES

3D MEMORY CELLS AND ARRAY ARCHITECTURES AND PROCESSES

ADVANCED STRUCTURES HAVING MOSFET TRANSISTORS AND METAL LAYERS

3D MEMORY CELLS AND ARRAY ARCHITECTURES

METHODS AND APPARATUS FOR NAND FLASH MEMORY

METHODS AND APPARATUS FOR A NOVEL MEMORY ARRAY

METHODS AND APPARATUS FOR NEURAL NETWORK ARRAYS

Configurable Three-Dimensional Neural Network Array

METHODS AND APPARATUS FOR NAND FLASH MEMORY

TRANSISTOR STRUCTURES AND ASSOCIATED PROCESSES

METHODS AND APPARATUS FOR NAND FLASH MEMORY

METHODS AND APPARATUS FOR NAND FLASH MEMORY

METHODS AND APPARATUS FOR NAND FLASH MEMORY

THREE DIMENSIONAL DOUBLE-DENSITY MEMORY ARRAY

QUANTUM BIT ARRAY