Fuji Yang

Person

Old Bridge, NJ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for improved phase linearity in a multi-phase...
- Patent number 7,808,329
- Issue date Oct 5, 2010
- Agere Systems Inc.
- Kameran Azadet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Duty cycle correction circuit for high-speed clock signals
- Patent number 7,733,143
- Issue date Jun 8, 2010
- Agere Systems Inc.
- Chunbing Guo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple frequency generator for quadrature amplitude modulated com...
- Patent number 7,598,815
- Issue date Oct 6, 2009
- Agere Systems Inc.
- Jinghong Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital phase-looked loop
- Patent number 7,577,225
- Issue date Aug 18, 2009
- Agere Systems Inc.
- Kameran Azadet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-channel serdes receiver for chip-to-chip and backplane interc...
- Patent number 7,426,247
- Issue date Sep 16, 2008
- Agere Systems Inc.
- Fuji Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Common-mode shifting circuit for CML buffers
- Patent number 7,355,451
- Issue date Apr 8, 2008
- Agere Systems Inc.
- Kameran Azadet
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for receiver detection on a PCI-Express bus
- Patent number 7,222,290
- Issue date May 22, 2007
- Agere Systems Inc.
- Chunbing Guo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable receive-side channel equalizer
- Patent number 7,164,711
- Issue date Jan 16, 2007
- Agere Systems Inc.
- Fuji Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-channel serdes receiver for chip-to-chip and backplane interc...
- Patent number 7,158,587
- Issue date Jan 2, 2007
- Agere Systems Inc.
- Fuji Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-level pulse amplitude modulation receiver
- Patent number 7,099,400
- Issue date Aug 29, 2006
- Agere Systems Inc.
- Fuji Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Four quadrant analog mixer-based delay-locked loop for clock and da...
- Patent number 6,586,977
- Issue date Jul 1, 2003
- Agere Systems Inc.
- Fuji Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Methods And Apparatus For Improved Phase Linearity In A Multi-Phase...
- Publication number 20100034333
- Publication date Feb 11, 2010
- Kameran Azadet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUTY CYCLE CORRECTION CIRCUIT FOR HIGH-SPEED CLOCK SIGNALS
- Publication number 20090160516
- Publication date Jun 25, 2009
- Agere Systems Inc.
- Chunbing Guo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE FREQUENCY GENERATOR FOR QUADRATURE AMPLITUDE MODULATED COM...
- Publication number 20080100387
- Publication date May 1, 2008
- Jinghong Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTI-CHANNEL SERDES RECEIVER FOR CHIP-TO-CHIP AND BACKPLANE INTERC...
- Publication number 20070092039
- Publication date Apr 26, 2007
- Agere Systems Incorporated
- Fuji Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digital phase-locked loop
- Publication number 20070025490
- Publication date Feb 1, 2007
- Agere Systems Inc.
- Kameran Azadet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Common-mode shifting circuit for CML buffers
- Publication number 20060017468
- Publication date Jan 26, 2006
- Agere Systems, Inc.
- Kameran Azadet
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for receiver detection on a PCI-Express bus
- Publication number 20050104623
- Publication date May 19, 2005
- Chunbing Guo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multi-level pulse amplitude modulation receiver
- Publication number 20040141567
- Publication date Jul 22, 2004
- Fuji Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable receive-side channel equalizer
- Publication number 20040141552
- Publication date Jul 22, 2004
- Fuji Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multi-channel serdes receiver for chip-to-chip and backplane interc...
- Publication number 20030053565
- Publication date Mar 20, 2003
- Fuji Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Four quadrant analog mixer-based delay-locked loop for clock and da...
- Publication number 20020097073
- Publication date Jul 25, 2002
- Agere Systems Inc.
- Fuji Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Person

Patents Grantslast 30 patents

Methods and apparatus for improved phase linearity in a multi-phase...

Duty cycle correction circuit for high-speed clock signals

Multiple frequency generator for quadrature amplitude modulated com...

Digital phase-looked loop

Multi-channel serdes receiver for chip-to-chip and backplane interc...

Common-mode shifting circuit for CML buffers

Method and apparatus for receiver detection on a PCI-Express bus

Programmable receive-side channel equalizer

Multi-channel serdes receiver for chip-to-chip and backplane interc...

Multi-level pulse amplitude modulation receiver

Four quadrant analog mixer-based delay-locked loop for clock and da...

Patents Applicationslast 30 patents

Methods And Apparatus For Improved Phase Linearity In A Multi-Phase...

DUTY CYCLE CORRECTION CIRCUIT FOR HIGH-SPEED CLOCK SIGNALS

MULTIPLE FREQUENCY GENERATOR FOR QUADRATURE AMPLITUDE MODULATED COM...

MULTI-CHANNEL SERDES RECEIVER FOR CHIP-TO-CHIP AND BACKPLANE INTERC...

Digital phase-locked loop

Common-mode shifting circuit for CML buffers

Method and apparatus for receiver detection on a PCI-Express bus

Multi-level pulse amplitude modulation receiver

Programmable receive-side channel equalizer

Multi-channel serdes receiver for chip-to-chip and backplane interc...

Four quadrant analog mixer-based delay-locked loop for clock and da...