Fulong Zhang

Person

Allentown, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Key provisioning systems and methods for programmable logic devices
- Patent number 12,197,581
- Issue date Jan 14, 2025
- Lattice Semiconductor Corporation
- Srirama Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure boot systems and methods for programmable logic devices
- Patent number 12,189,777
- Issue date Jan 7, 2025
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast boot systems and methods for programmable logic devices
- Patent number 12,093,701
- Issue date Sep 17, 2024
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Failure characterization systems and methods for erasing and debugg...
- Patent number 11,971,992
- Issue date Apr 30, 2024
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asset management systems and methods for programmable logic devices
- Patent number 11,914,716
- Issue date Feb 27, 2024
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast boot systems and methods for programmable logic devices
- Patent number 11,847,471
- Issue date Dec 19, 2023
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast boot systems and methods for programmable logic devices
- Patent number 11,681,536
- Issue date Jun 20, 2023
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast boot systems and methods for programmable logic devices
- Patent number 11,132,207
- Issue date Sep 28, 2021
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serializer with multiple stages
- Patent number 8,912,933
- Issue date Dec 16, 2014
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
In-system margin measurement circuit
- Patent number 8,686,773
- Issue date Apr 1, 2014
- Lattice Semiconductor Corporation
- Fulong Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power configurable delay element
- Patent number 8,461,894
- Issue date Jun 11, 2013
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Serializer with odd gearing ratio
- Patent number 8,274,412
- Issue date Sep 25, 2012
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-power, glitch-less, configurable delay element
- Patent number 8,248,136
- Issue date Aug 21, 2012
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flexible delay cell architecture
- Patent number 7,863,931
- Issue date Jan 4, 2011
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Distributed front-end FIFO for source-synchronous interfaces with n...
- Patent number 7,808,855
- Issue date Oct 5, 2010
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Jitter tolerant delay-locked loop circuit
- Patent number 7,620,839
- Issue date Nov 17, 2009
- Lattice Semiconductor Corporation
- Zheng (Jeff) Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed front-end FIFO for source-synchronized interfaces with...
- Patent number 7,573,770
- Issue date Aug 11, 2009
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital I/O timing control
- Patent number 7,495,495
- Issue date Feb 24, 2009
- Lattice Semiconductor Corporation
- Fulong Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronization of programmable multiplexers and demultiplexers
- Patent number 7,109,754
- Issue date Sep 19, 2006
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronization of programmable multiplexers and demultiplexers
- Patent number 7,109,756
- Issue date Sep 19, 2006
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock generation
- Patent number 7,091,763
- Issue date Aug 15, 2006
- Lattice Semiconductor Corporation
- Phillip Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable I/O interfaces for FPGAs and other PLDs
- Patent number 7,009,423
- Issue date Mar 7, 2006
- Lattice Semiconductor Corporation
- William B. Andrews
- G11 - INFORMATION STORAGE
Information Patent Grant
Digitally controlled delay cells
- Patent number 7,009,433
- Issue date Mar 7, 2006
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with integrated standard-cell logic blocks
- Patent number 6,975,137
- Issue date Dec 13, 2005
- Lattice Semiconductor Corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable I/O interfaces for FPGAs and other PLDs
- Patent number 6,952,115
- Issue date Oct 4, 2005
- Lattice Semiconductor Corporation
- William B. Andrews
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory access via serial memory interface
- Patent number 6,903,574
- Issue date Jun 7, 2005
- Lattice Semiconductor Corporation
- Zheng (Jeff) Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic devices with integrated standard-cell logic blocks
- Patent number 6,870,395
- Issue date Mar 22, 2005
- Lattice Semiconductor Corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronization of programmable multiplexers and demultiplexers
- Patent number 6,856,171
- Issue date Feb 15, 2005
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
TAMPER DETECTION SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20240232439
- Publication date Jul 11, 2024
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20230367610
- Publication date Nov 16, 2023
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20220012064
- Publication date Jan 13, 2022
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20210173669
- Publication date Jun 10, 2021
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAILURE CHARACTERIZATION SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC...
- Publication number 20210081578
- Publication date Mar 18, 2021
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASSET MANAGEMENT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20210081577
- Publication date Mar 18, 2021
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20210081536
- Publication date Mar 18, 2021
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
KEY PROVISIONING SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20210083675
- Publication date Mar 18, 2021
- Lattice Semiconductor Corporation
- Srirama Chandra
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20190205144
- Publication date Jul 4, 2019
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Jitter tolerant delay-locked loop circuit
- Publication number 20070136619
- Publication date Jun 14, 2007
- Zheng (Jeff) Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital I/O timing control
- Publication number 20070109880
- Publication date May 17, 2007
- Fulong Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
Memory access via serial memory interface
- Publication number 20050024085
- Publication date Feb 3, 2005
- Zheng (Jeff) Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digitally controlled delay cells
- Publication number 20040239387
- Publication date Dec 2, 2004
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic devices with integrated standard-cell logic blocks
- Publication number 20040183564
- Publication date Sep 23, 2004
- Lattice Semiconductor Corporation, a Delaware corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY

Fulong Zhang

Person

Patents Grantslast 30 patents

Key provisioning systems and methods for programmable logic devices

Secure boot systems and methods for programmable logic devices

Fast boot systems and methods for programmable logic devices

Failure characterization systems and methods for erasing and debugg...

Asset management systems and methods for programmable logic devices

Fast boot systems and methods for programmable logic devices

Fast boot systems and methods for programmable logic devices

Fast boot systems and methods for programmable logic devices

Serializer with multiple stages

In-system margin measurement circuit

Low-power configurable delay element

Serializer with odd gearing ratio

Low-power, glitch-less, configurable delay element

Flexible delay cell architecture

Distributed front-end FIFO for source-synchronous interfaces with n...

Jitter tolerant delay-locked loop circuit

Distributed front-end FIFO for source-synchronized interfaces with...

Digital I/O timing control

Synchronization of programmable multiplexers and demultiplexers

Synchronization of programmable multiplexers and demultiplexers

Clock generation

Programmable I/O interfaces for FPGAs and other PLDs

Digitally controlled delay cells

Programmable logic devices with integrated standard-cell logic blocks

Programmable I/O interfaces for FPGAs and other PLDs

Memory access via serial memory interface

Programmable logic devices with integrated standard-cell logic blocks

Synchronization of programmable multiplexers and demultiplexers

Patents Applicationslast 30 patents

TAMPER DETECTION SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

FAILURE CHARACTERIZATION SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC...

ASSET MANAGEMENT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

SECURE BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

KEY PROVISIONING SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

Jitter tolerant delay-locked loop circuit

Digital I/O timing control

Memory access via serial memory interface

Digitally controlled delay cells

Programmable logic devices with integrated standard-cell logic blocks