Fung Fung Lee

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Generation of graphical design representation from a design specifi...
- Patent number 7,412,669
- Issue date Aug 12, 2008
- Xilinx, Inc.
- Fung Fung Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable processor system unit
- Patent number 6,467,009
- Issue date Oct 15, 2002
- Triscend Corporation
- Steven Paul Winegarden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bank-based configuration and reconfiguration for programmable logic...
- Patent number 6,459,646
- Issue date Oct 1, 2002
- Triscend Corporation
- Wilson Yee
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for incremental timing analysis
- Patent number 6,367,056
- Issue date Apr 2, 2002
- Altera Corporation
- Fung Fung Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic array integrated circuit architectures
- Patent number 6,366,121
- Issue date Apr 2, 2002
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hierarchical circuit partitioning using sliding windows
- Patent number 6,301,694
- Issue date Oct 9, 2001
- Altera Corporation
- Fung Fung Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gain matrix for hierarchical circuit partitioning
- Patent number 6,212,668
- Issue date Apr 3, 2001
- Altera Corporation
- John Tse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fitting for incremental compilation of electronic designs
- Patent number 6,102,964
- Issue date Aug 15, 2000
- Altera Corporation
- John Tse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device architectures
- Patent number 5,982,195
- Issue date Nov 9, 1999
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic array integrated circuit architectures
- Patent number 5,963,049
- Issue date Oct 5, 1999
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic array integrated circuit devices with interleave...
- Patent number 5,909,126
- Issue date Jun 1, 1999
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic array integrated circuits
- Patent number 5,883,850
- Issue date Mar 16, 1999
- Altera Corporation
- Fung Fung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Interleaved interconnect for programmable logic array devices
- Patent number 5,880,597
- Issue date Mar 9, 1999
- Altera Corporation
- Fung Fung Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with two dimensional memory addressing
- Patent number 5,844,854
- Issue date Dec 1, 1998
- Altera Corporation
- Fung Fung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic array integrated circuits with carry and/or casc...
- Patent number 5,672,985
- Issue date Sep 30, 1997
- Altera Corporation
- Fung Fung Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic array integrated circuit devices with flexible c...
- Patent number 5,631,576
- Issue date May 20, 1997
- Altera Corporation
- Fung F. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR INCREMENTAL TIMING ANALYSIS
- Publication number 20020023252
- Publication date Feb 21, 2002
- FUNG FUNG LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic array integrated circuit architectures
- Publication number 20010022519
- Publication date Sep 20, 2001
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY

Fung Fung Lee

Person

Patents Grantslast 30 patents

Generation of graphical design representation from a design specifi...

Configurable processor system unit

Bank-based configuration and reconfiguration for programmable logic...

Method for incremental timing analysis

Programmable logic array integrated circuit architectures

Hierarchical circuit partitioning using sliding windows

Gain matrix for hierarchical circuit partitioning

Fitting for incremental compilation of electronic designs

Programmable logic device architectures

Programmable logic array integrated circuit architectures

Programmable logic array integrated circuit devices with interleave...

Programmable logic array integrated circuits

Interleaved interconnect for programmable logic array devices

Programmable logic device with two dimensional memory addressing

Programmable logic array integrated circuits with carry and/or casc...

Programmable logic array integrated circuit devices with flexible c...

Patents Applicationslast 30 patents

METHOD FOR INCREMENTAL TIMING ANALYSIS

Programmable logic array integrated circuit architectures