Gabor Drasny

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Clock-gating phase algebra for clock analysis
- Patent number 10,990,725
- Issue date Apr 27, 2021
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design analyzer
- Patent number 10,599,792
- Issue date Mar 24, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for virtual clock and mode extraction in hierarchical...
- Patent number 10,558,782
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Glitch-aware phase algebra for clock analysis
- Patent number 10,552,559
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional phase algebra for clock analysis
- Patent number 10,552,558
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock-gating phase algebra for clock analysis
- Patent number 10,515,164
- Issue date Dec 24, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for specifying clocks and modes in hierarchical designs
- Patent number 10,503,856
- Issue date Dec 10, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock-gating phase algebra for clock analysis
- Patent number 10,331,822
- Issue date Jun 25, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional phase algebra for clock analysis
- Patent number 10,325,040
- Issue date Jun 18, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design analyzer
- Patent number 10,325,041
- Issue date Jun 18, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for virtual clock and mode extraction in hierarchical...
- Patent number 10,318,695
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for analysis of hierarchical designs
- Patent number 10,216,881
- Issue date Feb 26, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for analysis of hierarchical designs
- Patent number 9,916,407
- Issue date Mar 13, 2018
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Glitch-aware phase algebra for clock analysis
- Patent number 9,830,412
- Issue date Nov 28, 2017
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for analysis of hierarchical designs
- Patent number 9,798,844
- Issue date Oct 24, 2017
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static checking of asynchronous clock domain crossings
- Patent number 9,547,732
- Issue date Jan 17, 2017
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for static checking of asynchronous clock domain crossings
- Patent number 9,536,024
- Issue date Jan 3, 2017
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design evaluation with compact multi-waveform representations
- Patent number 9,251,304
- Issue date Feb 2, 2016
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesizing VHDL multiple wait FSMS into RT level FSMS by preproce...
- Patent number 8,713,494
- Issue date Apr 29, 2014
- International Business Machines Corporation
- Gabor Bobok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs...
- Patent number 8,495,533
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler option consistency checking during incremental hardware de...
- Patent number 8,230,406
- Issue date Jul 24, 2012
- International Business Machines Corporation
- Richard L. H. Carbone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for modeling variables in subprograms of hardware descri...
- Patent number 8,140,313
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unrolling hardware design generate statements in a source window de...
- Patent number 7,823,097
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and program product for pre-compile processing of h...
- Patent number 7,506,287
- Issue date Mar 17, 2009
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for encoding binary data as a zero terminated...
- Patent number 7,280,055
- Issue date Oct 9, 2007
- International Business Machines Corporation
- Gabor Drasny
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
ITERATIVE DESIGN OF AN INTEGRATED CIRCUIT DESIGN
- Publication number 20230074528
- Publication date Mar 9, 2023
- International Business Machines Corporation
- Ali S. El-Zein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK-GATING PHASE ALGEBRA FOR CLOCK ANALYSIS
- Publication number 20190266302
- Publication date Aug 29, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALGEBRA FOR VIRTUAL CLOCK AND MODE EXTRACTION IN HIERARCHICAL...
- Publication number 20190258772
- Publication date Aug 22, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALGEBRA FOR ANALYSIS OF HIERARCHICAL DESIGNS
- Publication number 20180107776
- Publication date Apr 19, 2018
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN ANALYZER
- Publication number 20180082003
- Publication date Mar 22, 2018
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS
- Publication number 20180075178
- Publication date Mar 15, 2018
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALGEBRA FOR SPECIFYING CLOCKS AND MODES IN HIERARCHICAL DESIGNS
- Publication number 20160188760
- Publication date Jun 30, 2016
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALGEBRA FOR VIRTUAL CLOCK AND MODE EXTRACTION IN HIERARCHICAL...
- Publication number 20160188785
- Publication date Jun 30, 2016
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONDITIONAL PHASE ALGEBRA FOR CLOCK ANALYSIS
- Publication number 20160078162
- Publication date Mar 17, 2016
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS
- Publication number 20150370939
- Publication date Dec 24, 2015
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK-GATING PHASE ALGEBRA FOR CLOCK ANALYSIS
- Publication number 20150370940
- Publication date Dec 24, 2015
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALGEBRA FOR ANALYSIS OF HIERARCHICAL DESIGNS
- Publication number 20150269299
- Publication date Sep 24, 2015
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC CHECKING OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS
- Publication number 20150269296
- Publication date Sep 24, 2015
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALGEBRA FOR ANALYSIS OF HIERARCHICAL DESIGNS
- Publication number 20150169816
- Publication date Jun 18, 2015
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC CHECKING OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS
- Publication number 20150161312
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN EVALUATION WITH COMPACT MULTI-WAVEFORM REPRESENTATIONS
- Publication number 20150161313
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONDITIONAL PHASE ALGEBRA FOR CLOCK ANALYSIS
- Publication number 20150161311
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS
- Publication number 20150161309
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK-GATING PHASE ALGEBRA FOR CLOCK ANALYSIS
- Publication number 20150161310
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNTHESIZING VHDL MULTIPLE WAIT FSMS INTO RT LEVEL FSMS BY PREPROCE...
- Publication number 20130275930
- Publication date Oct 17, 2013
- Gabor Bobok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR MODELING VARIABLES IN SUBPROGRAMS OF HARDWARE DESCRI...
- Publication number 20090193390
- Publication date Jul 30, 2009
- GABOR DRASNY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs...
- Publication number 20080127126
- Publication date May 29, 2008
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compiler Option Consistency Checking During Incremental Hardware De...
- Publication number 20080127130
- Publication date May 29, 2008
- International Business Machines Corporation
- Richard L.H. Carbone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, system, and program product for pre-compile processing of H...
- Publication number 20080072187
- Publication date Mar 20, 2008
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Unrolling Hardware Design Generate Statements in a Source Window De...
- Publication number 20080072206
- Publication date Mar 20, 2008
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for encoding binary data as a zero terminated...
- Publication number 20070052563
- Publication date Mar 8, 2007
- International Business Machines Corporation
- Gabor Drasny
- H03 - BASIC ELECTRONIC CIRCUITRY

Gabor Drasny

Person

Patents Grantslast 30 patents

Clock-gating phase algebra for clock analysis

Circuit design analyzer

Phase algebra for virtual clock and mode extraction in hierarchical...

Glitch-aware phase algebra for clock analysis

Conditional phase algebra for clock analysis

Clock-gating phase algebra for clock analysis

Phase algebra for specifying clocks and modes in hierarchical designs

Clock-gating phase algebra for clock analysis

Conditional phase algebra for clock analysis

Circuit design analyzer

Phase algebra for virtual clock and mode extraction in hierarchical...

Phase algebra for analysis of hierarchical designs

Phase algebra for analysis of hierarchical designs

Glitch-aware phase algebra for clock analysis

Phase algebra for analysis of hierarchical designs

Static checking of asynchronous clock domain crossings

Methods for static checking of asynchronous clock domain crossings

Circuit design evaluation with compact multi-waveform representations

Synthesizing VHDL multiple wait FSMS into RT level FSMS by preproce...

Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs...

Compiler option consistency checking during incremental hardware de...

Techniques for modeling variables in subprograms of hardware descri...

Unrolling hardware design generate statements in a source window de...

Method, system, and program product for pre-compile processing of h...

Method and apparatus for encoding binary data as a zero terminated...

Patents Applicationslast 30 patents

ITERATIVE DESIGN OF AN INTEGRATED CIRCUIT DESIGN

CLOCK-GATING PHASE ALGEBRA FOR CLOCK ANALYSIS

PHASE ALGEBRA FOR VIRTUAL CLOCK AND MODE EXTRACTION IN HIERARCHICAL...

PHASE ALGEBRA FOR ANALYSIS OF HIERARCHICAL DESIGNS

CIRCUIT DESIGN ANALYZER

GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS

PHASE ALGEBRA FOR SPECIFYING CLOCKS AND MODES IN HIERARCHICAL DESIGNS

PHASE ALGEBRA FOR VIRTUAL CLOCK AND MODE EXTRACTION IN HIERARCHICAL...

CONDITIONAL PHASE ALGEBRA FOR CLOCK ANALYSIS

GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS

CLOCK-GATING PHASE ALGEBRA FOR CLOCK ANALYSIS

PHASE ALGEBRA FOR ANALYSIS OF HIERARCHICAL DESIGNS

STATIC CHECKING OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS

PHASE ALGEBRA FOR ANALYSIS OF HIERARCHICAL DESIGNS

STATIC CHECKING OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS

CIRCUIT DESIGN EVALUATION WITH COMPACT MULTI-WAVEFORM REPRESENTATIONS

CONDITIONAL PHASE ALGEBRA FOR CLOCK ANALYSIS

GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS

CLOCK-GATING PHASE ALGEBRA FOR CLOCK ANALYSIS

SYNTHESIZING VHDL MULTIPLE WAIT FSMS INTO RT LEVEL FSMS BY PREPROCE...

TECHNIQUES FOR MODELING VARIABLES IN SUBPROGRAMS OF HARDWARE DESCRI...

Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs...

Compiler Option Consistency Checking During Incremental Hardware De...

Method, system, and program product for pre-compile processing of H...

Unrolling Hardware Design Generate Statements in a Source Window De...

Method and apparatus for encoding binary data as a zero terminated...