Gael Paul

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Palo Alto, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Automated bottom-up and top-down partitioned design synthesis
- Patent number 10,296,689
- Issue date May 21, 2019
- Synopsys, Inc.
- Smita Bakshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for circuit design and optimization
- Patent number 9,280,632
- Issue date Mar 8, 2016
- Synopsys, Inc.
- Saurabh Adya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated bottom-up and top-down partitioned design synthesis
- Patent number 8,082,138
- Issue date Dec 20, 2011
- Synopsys, Inc.
- Smita Bakshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Skew reduction for generated clocks
- Patent number 7,500,205
- Issue date Mar 3, 2009
- Synopsys, Inc.
- Gael Paul
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Circuit Design and Optimization
- Publication number 20160188774
- Publication date Jun 30, 2016
- Synopsys, Inc.
- Saurabh Adya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automated Bottom-Up and Top-Down Partitioned Design Synthesis
- Publication number 20150012898
- Publication date Jan 8, 2015
- Synopsys, Inc.
- Smita Bakshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automated Bottom-Up and Top-Down Partitioned Design Synthesis
- Publication number 20120089956
- Publication date Apr 12, 2012
- Smita Bakshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Skew reduction for generated clocks
- Publication number 20060129961
- Publication date Jun 15, 2006
- Gael Paul
- G06 - COMPUTING CALCULATING COUNTING