Gang Chen

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Compiler assisted register file write reduction
- Patent number 11,900,502
- Issue date Feb 13, 2024
- Intel Corporation
- Chandra S. Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtualization and multi-tenancy support in graphics processors
- Patent number 11,748,130
- Issue date Sep 5, 2023
- Intel Corporation
- Rajesh Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control flow mechanism for execution of graphics processor instruct...
- Patent number 11,537,403
- Issue date Dec 27, 2022
- Intel Corporation
- Subramaniam M. Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler assisted register file write reduction
- Patent number 11,321,799
- Issue date May 3, 2022
- Intel Corporation
- Chandra S. Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control flow mechanism for execution of graphics processor instruct...
- Patent number 10,990,409
- Issue date Apr 27, 2021
- Intel Corporation
- Subramaniam M. Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing analysis with double pattern lithography
- Patent number 8,856,697
- Issue date Oct 7, 2014
- Synopsys, Inc.
- Jianfeng Luo
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
VIRTUALIZATION AND MULTI-TENANCY SUPPORT IN GRAPHICS PROCESSORS
- Publication number 20240061700
- Publication date Feb 22, 2024
- Intel Corporation
- Rajesh SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPILER ASSISTED REGISTER FILE WRITE REDUCTION
- Publication number 20220261949
- Publication date Aug 18, 2022
- Intel Corporation
- Chandra S. GURRAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROL FLOW MECHANISM FOR EXECUTION OF GRAPHICS PROCESSOR INSTRUCT...
- Publication number 20210286626
- Publication date Sep 16, 2021
- Intel Corporation
- Subramaniam M. Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPILER ASSISTED REGISTER FILE WRITE REDUCTION
- Publication number 20210192673
- Publication date Jun 24, 2021
- Intel Corporation
- Chandra S. GURRAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEEP LEARNING IMPLEMENTATIONS USING SYSTOLIC ARRAYS AND FUSED OPERA...
- Publication number 20210089316
- Publication date Mar 25, 2021
- Intel Corporation
- William RASH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUALIZATION AND MULTI-TENANCY SUPPORT IN GRAPHICS PROCESSORS
- Publication number 20200409733
- Publication date Dec 31, 2020
- Rajesh SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS CONTROL FLOW MECHANISM
- Publication number 20180307487
- Publication date Oct 25, 2018
- Subramaniam M. Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMD CHANNEL UTILIZATION UNDER DIVERGENT CONTROL FLOW
- Publication number 20180121202
- Publication date May 3, 2018
- Intel Corporation
- Gang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Increasing Thread Payload for 3D Pipeline with Wider SIMD Execution...
- Publication number 20170178384
- Publication date Jun 22, 2017
- Jayashree Venkatesh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROUTING ANALYSIS WITH DOUBLE PATTERN LITHOGRAPHY
- Publication number 20120216157
- Publication date Aug 23, 2012
- Jianfeng Luo
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Compiler assisted register file write reduction

Virtualization and multi-tenancy support in graphics processors

Control flow mechanism for execution of graphics processor instruct...

Compiler assisted register file write reduction

Control flow mechanism for execution of graphics processor instruct...

Routing analysis with double pattern lithography

Patents Applicationslast 30 patents

VIRTUALIZATION AND MULTI-TENANCY SUPPORT IN GRAPHICS PROCESSORS

COMPILER ASSISTED REGISTER FILE WRITE REDUCTION

CONTROL FLOW MECHANISM FOR EXECUTION OF GRAPHICS PROCESSOR INSTRUCT...

COMPILER ASSISTED REGISTER FILE WRITE REDUCTION

DEEP LEARNING IMPLEMENTATIONS USING SYSTOLIC ARRAYS AND FUSED OPERA...

VIRTUALIZATION AND MULTI-TENANCY SUPPORT IN GRAPHICS PROCESSORS

GRAPHICS CONTROL FLOW MECHANISM

SIMD CHANNEL UTILIZATION UNDER DIVERGENT CONTROL FLOW

Increasing Thread Payload for 3D Pipeline with Wider SIMD Execution...

ROUTING ANALYSIS WITH DOUBLE PATTERN LITHOGRAPHY