Gary A. Van Huben

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Host synchronized autonomous data chip address sequencer for a dist...
- Patent number 11,687,254
- Issue date Jun 27, 2023
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address/command chip controlled data chip address sequencing for a...
- Patent number 11,587,600
- Issue date Feb 21, 2023
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packeted protocol device test system
- Patent number 11,442,829
- Issue date Sep 13, 2022
- International Business Machines Corporation
- Ryan Patrick King
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address/command chip synchronized autonomous data chip address sequ...
- Patent number 11,379,123
- Issue date Jul 5, 2022
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing latency of memory read operations returning data on a read...
- Patent number 11,099,601
- Issue date Aug 24, 2021
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of a cyclic redundancy code multiple-input shift register to pr...
- Patent number 11,088,782
- Issue date Aug 10, 2021
- International Business Machines Corporation
- Steven R. Carlough
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Address/command chip synchronized autonomous data chip address sequ...
- Patent number 10,976,939
- Issue date Apr 13, 2021
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing chip latency at a clock boundary by reference clock phase...
- Patent number 10,771,068
- Issue date Sep 8, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host controlled data chip address sequencing for a distributed memo...
- Patent number 10,747,442
- Issue date Aug 18, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing latency of memory read operations returning data on a read...
- Patent number 10,698,440
- Issue date Jun 30, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable data collection for system management
- Patent number 10,649,511
- Issue date May 12, 2020
- International Business Machines Corporation
- Irving G Baysah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register access in a distributed memory buffer system
- Patent number 10,642,535
- Issue date May 5, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of a cyclic redundancy code multiple-input shift register to pr...
- Patent number 10,541,782
- Issue date Jan 21, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Host synchronized autonomous data chip address sequencer for a dist...
- Patent number 10,534,555
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically adjustable cyclic redundancy code types
- Patent number 10,530,396
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically adjustable cyclic redundancy code rates
- Patent number 10,530,523
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Address/command chip synchronized autonomous data chip address sequ...
- Patent number 10,489,069
- Issue date Nov 26, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of multiple cyclic redundancy codes for optimized fail isolation
- Patent number 10,419,035
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Address/command chip controlled data chip address sequencing for a...
- Patent number 10,395,698
- Issue date Aug 27, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
JTAG support over a broadcast bus in a distributed memory buffer sy...
- Patent number 10,393,805
- Issue date Aug 27, 2019
- International Business Machines Corporation
- Logan I. Friedman
- G01 - MEASURING TESTING
Information Patent Grant
Partial data replay in a distributed memory buffer system
- Patent number 10,353,606
- Issue date Jul 16, 2019
- International Business Machines Corporation
- Susan M. Eickhoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable data collection for system management
- Patent number 10,317,964
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Irving G Baysah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double data rate (DDR) memory read latency reduction
- Patent number 10,162,773
- Issue date Dec 25, 2018
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient calibration of a data eye for memory devices
- Patent number 10,134,455
- Issue date Nov 20, 2018
- International Business Machines Corporation
- John S. Bialas
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Simultaneous write, read, and command-address-control calibration o...
- Patent number 10,090,065
- Issue date Oct 2, 2018
- International Business Machines Corporation
- Stephen P. Glancy
- G11 - INFORMATION STORAGE
Information Patent Grant
Partial data replay in a distributed memory buffer system
- Patent number 10,078,461
- Issue date Sep 18, 2018
- International Business Machines Corporation
- Susan M. Eickhoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simultaneous write and read calibration of an interface within a ci...
- Patent number 10,068,634
- Issue date Sep 4, 2018
- International Business Machines Corporation
- Stephen P. Glancy
- G11 - INFORMATION STORAGE
Information Patent Grant
Physically aware test patterns in semiconductor fabrication
- Patent number 10,061,886
- Issue date Aug 28, 2018
- International Business Machines Corporation
- William V. Huott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physically aware test patterns in semiconductor fabrication
- Patent number 9,922,163
- Issue date Mar 20, 2018
- International Business Machines Corporation
- William V. Huott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient calibration of a data eye for memory devices
- Patent number 9,899,067
- Issue date Feb 20, 2018
- International Business Machines Corporation
- John S. Bialas
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CROSS-LAYER POWER OPTIMIZATION OF PROGRAM CODE AND/OR SOFTWARE ARCH...
- Publication number 20240419417
- Publication date Dec 19, 2024
- International Business Machines Corporation
- Dinesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKETED PROTOCOL DEVICE TEST SYSTEM
- Publication number 20210286694
- Publication date Sep 16, 2021
- International Business Machines Corporation
- Ryan Patrick King
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...
- Publication number 20210191630
- Publication date Jun 24, 2021
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...
- Publication number 20200119843
- Publication date Apr 16, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HOST SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQUENCER FOR A DIST...
- Publication number 20200073565
- Publication date Mar 5, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...
- Publication number 20200042205
- Publication date Feb 6, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...
- Publication number 20190384352
- Publication date Dec 19, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING CHIP LATENCY AT A CLOCK BOUNDARY BY REFERENCE CLOCK PHASE...
- Publication number 20190260380
- Publication date Aug 22, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE DATA COLLECTION FOR SYSTEM MANAGEMENT
- Publication number 20190250682
- Publication date Aug 15, 2019
- International Business Machines Corporation
- Irving G. Baysah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address/Command Chip Controlled Data Chip Address Sequencing for a...
- Publication number 20190252010
- Publication date Aug 15, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register Access in a Distributed Memory Buffer System
- Publication number 20190227741
- Publication date Jul 25, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...
- Publication number 20190212769
- Publication date Jul 11, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JTAG SUPPORT OVER A BROADCAST BUS IN A DISTRIBUTED MEMORY BUFFER SY...
- Publication number 20190170819
- Publication date Jun 6, 2019
- International Business Machines Corporation
- Logan I. Friedman
- G01 - MEASURING TESTING
Information Patent Application
Host Controlled Data Chip Address Sequencing for a Distributed Memo...
- Publication number 20190163362
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address/Command Chip Synchronized Autonomous Data Chip Address Sequ...
- Publication number 20190163378
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Host Synchronized Autonomous Data Chip Address Sequencer for A Dist...
- Publication number 20190163384
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address/Command Chip Controlled Data Chip Address Sequencing for A...
- Publication number 20190163383
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE TYPES
- Publication number 20190158125
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE RATES
- Publication number 20190158218
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...
- Publication number 20190158223
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
USE OF MULTIPLE CYCLIC REDUNDANCY CODES FOR OPTIMIZED FAIL ISOLATION
- Publication number 20190158126
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PARTIAL DATA REPLAY IN A DISTRIBUTED MEMORY BUFFER SYSTEM
- Publication number 20190114091
- Publication date Apr 18, 2019
- International Business Machines Corporation
- Susan M. Eickhoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULTANEOUS WRITE, READ, AND COMMAND-ADDRESS-CONTROL CALIBRATION O...
- Publication number 20180322939
- Publication date Nov 8, 2018
- STEPHEN P. GLANCY
- G11 - INFORMATION STORAGE
Information Patent Application
SIMULTANEOUS WRITE, READ, AND COMMAND-ADDRESS-CONTROL CALIBRATION O...
- Publication number 20180268918
- Publication date Sep 20, 2018
- International Business Machines Corporation
- STEPHEN P. GLANCY
- G11 - INFORMATION STORAGE
Information Patent Application
PHYSICALLY AWARE TEST PATTERNS IN SEMICONDUCTOR FABRICATION
- Publication number 20180101638
- Publication date Apr 12, 2018
- International Business Machines Corporation
- William V. Huott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT CALIBRATION OF MEMORY DEVICES
- Publication number 20180075887
- Publication date Mar 15, 2018
- International Business Machines Corporation
- John S. Bialas
- G11 - INFORMATION STORAGE
Information Patent Application
PHYSICALLY AWARE TEST PATTERNS IN SEMICONDUCTOR FABRICATION
- Publication number 20180011962
- Publication date Jan 11, 2018
- International Business Machines Corporation
- William V. Huott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULTANEOUS WRITE AND READ CALIBRATION OF AN INTERFACE WITHIN A CI...
- Publication number 20170270994
- Publication date Sep 21, 2017
- International Business Machines Corporation
- STEPHEN P. GLANCY
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENT CALIBRATION OF MEMORY DEVICES
- Publication number 20170178703
- Publication date Jun 22, 2017
- International Business Machines Corporation
- John S. Bialas
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENT CALIBRATION OF MEMORY DEVICES
- Publication number 20170154660
- Publication date Jun 1, 2017
- International Business Machines Corporation
- John S. Bialas
- G11 - INFORMATION STORAGE

Gary A. Van Huben

Person

Patents Grantslast 30 patents

Host synchronized autonomous data chip address sequencer for a dist...

Address/command chip controlled data chip address sequencing for a...

Packeted protocol device test system

Address/command chip synchronized autonomous data chip address sequ...

Reducing latency of memory read operations returning data on a read...

Use of a cyclic redundancy code multiple-input shift register to pr...

Address/command chip synchronized autonomous data chip address sequ...

Reducing chip latency at a clock boundary by reference clock phase...

Host controlled data chip address sequencing for a distributed memo...

Reducing latency of memory read operations returning data on a read...

Scalable data collection for system management

Register access in a distributed memory buffer system

Use of a cyclic redundancy code multiple-input shift register to pr...

Host synchronized autonomous data chip address sequencer for a dist...

Dynamically adjustable cyclic redundancy code types

Dynamically adjustable cyclic redundancy code rates

Address/command chip synchronized autonomous data chip address sequ...

Use of multiple cyclic redundancy codes for optimized fail isolation

Address/command chip controlled data chip address sequencing for a...

JTAG support over a broadcast bus in a distributed memory buffer sy...

Partial data replay in a distributed memory buffer system

Scalable data collection for system management

Double data rate (DDR) memory read latency reduction

Efficient calibration of a data eye for memory devices

Simultaneous write, read, and command-address-control calibration o...

Partial data replay in a distributed memory buffer system

Simultaneous write and read calibration of an interface within a ci...

Physically aware test patterns in semiconductor fabrication

Physically aware test patterns in semiconductor fabrication

Efficient calibration of a data eye for memory devices

Patents Applicationslast 30 patents

CROSS-LAYER POWER OPTIMIZATION OF PROGRAM CODE AND/OR SOFTWARE ARCH...

PACKETED PROTOCOL DEVICE TEST SYSTEM

ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...

USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...

HOST SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQUENCER FOR A DIST...

ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...

REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...

REDUCING CHIP LATENCY AT A CLOCK BOUNDARY BY REFERENCE CLOCK PHASE...

SCALABLE DATA COLLECTION FOR SYSTEM MANAGEMENT

Address/Command Chip Controlled Data Chip Address Sequencing for a...

Register Access in a Distributed Memory Buffer System

REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...

JTAG SUPPORT OVER A BROADCAST BUS IN A DISTRIBUTED MEMORY BUFFER SY...

Host Controlled Data Chip Address Sequencing for a Distributed Memo...

Address/Command Chip Synchronized Autonomous Data Chip Address Sequ...

Host Synchronized Autonomous Data Chip Address Sequencer for A Dist...

Address/Command Chip Controlled Data Chip Address Sequencing for A...

DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE TYPES

DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE RATES

USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...

USE OF MULTIPLE CYCLIC REDUNDANCY CODES FOR OPTIMIZED FAIL ISOLATION

PARTIAL DATA REPLAY IN A DISTRIBUTED MEMORY BUFFER SYSTEM

SIMULTANEOUS WRITE, READ, AND COMMAND-ADDRESS-CONTROL CALIBRATION O...

SIMULTANEOUS WRITE, READ, AND COMMAND-ADDRESS-CONTROL CALIBRATION O...

PHYSICALLY AWARE TEST PATTERNS IN SEMICONDUCTOR FABRICATION

EFFICIENT CALIBRATION OF MEMORY DEVICES

PHYSICALLY AWARE TEST PATTERNS IN SEMICONDUCTOR FABRICATION

SIMULTANEOUS WRITE AND READ CALIBRATION OF AN INTERFACE WITHIN A CI...

EFFICIENT CALIBRATION OF MEMORY DEVICES

EFFICIENT CALIBRATION OF MEMORY DEVICES