Gary J. Lavelle

Person

Newtown, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and an apparatus with a sideband interface interconnecting...
- Patent number 9,753,875
- Issue date Sep 5, 2017
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memories utilizing hybrid error correcting code techniques
- Patent number 9,612,901
- Issue date Apr 4, 2017
- Intel Corporation
- Joshua D. Ruggiero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggregating completion messages in a sideband interface
- Patent number 9,270,576
- Issue date Feb 23, 2016
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Aggregating completion messages in a sideband interface
- Patent number 8,711,875
- Issue date Apr 29, 2014
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory controller with bank sorting and scheduling
- Patent number 7,698,498
- Issue date Apr 13, 2010
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for displaying multiple windows on a display m...
- Patent number 5,940,089
- Issue date Aug 17, 1999
- ATI Technologies
- Stephen C. Dilliplane
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Method and apparatus for translating addresses using mask and repla...
- Patent number 5,649,142
- Issue date Jul 15, 1997
- Intel Corporation
- Gary Lavelle
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE
- Publication number 20160132447
- Publication date May 12, 2016
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE
- Publication number 20140258492
- Publication date Sep 11, 2014
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORIES UTILIZING HYBRID ERROR CORRECTING CODE TECHNIQUES
- Publication number 20130262958
- Publication date Oct 3, 2013
- JOSHUA D. RUGGIERO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Aggregating Completion Messages In A Sideband Interface
- Publication number 20130083794
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller with bank sorting and scheduling
- Publication number 20070156946
- Publication date Jul 5, 2007
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING

Gary J. Lavelle

Person

Patents Grantslast 30 patents

Systems and an apparatus with a sideband interface interconnecting...

Memories utilizing hybrid error correcting code techniques

Aggregating completion messages in a sideband interface

Aggregating completion messages in a sideband interface

Memory controller with bank sorting and scheduling

Method and apparatus for displaying multiple windows on a display m...

Method and apparatus for translating addresses using mask and repla...

Patents Applicationslast 30 patents

AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE

AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE

MEMORIES UTILIZING HYBRID ERROR CORRECTING CODE TECHNIQUES

Aggregating Completion Messages In A Sideband Interface

Memory controller with bank sorting and scheduling