Gary L. McAlpine

Person

Banks, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Directional and priority based flow control mechanism between nodes
- Patent number 7,903,552
- Issue date Mar 8, 2011
- Intel Corporation
- Gary L. McAlpine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multiple-domain processing system using hierarchically orthogonal s...
- Patent number 7,808,989
- Issue date Oct 5, 2010
- Oleg Awsienko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Congestion control in a network
- Patent number 7,733,770
- Issue date Jun 8, 2010
- Intel Corporation
- Gary McAlpine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Directional and priority based flow control mechanism between nodes
- Patent number 7,457,245
- Issue date Nov 25, 2008
- Intel Corporation
- Gary McAlpine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multiple-domain processing system using hierarchically orthogonal s...
- Patent number 7,310,319
- Issue date Dec 18, 2007
- Intel Corporation
- Oleg Awsienko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Embedded transport acceleration architecture
- Patent number 7,305,493
- Issue date Dec 4, 2007
- Intel Corporation
- Gary L. McAlpine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for parallel processing of network data on a s...
- Patent number 7,000,048
- Issue date Feb 14, 2006
- Intel Corporation
- Gary L. McAlpine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical interrupt structure for event notification on multi-vi...
- Patent number 6,070,219
- Issue date May 30, 2000
- Intel Corporation
- Gary Lester McAlpine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Adaptive transmit rate control scheduler
- Patent number 6,011,798
- Issue date Jan 4, 2000
- Intel Corporation
- Gary McAlpine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
DIRECTIONAL AND PRIORITY BASED FLOW CONTROL MECHANISM BETWEEN NODES
- Publication number 20090073882
- Publication date Mar 19, 2009
- Intel Corporation
- Gary McAlpine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multiple-domain processing system using hierarchically orthogonal s...
- Publication number 20080144619
- Publication date Jun 19, 2008
- Oleg Awsienko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Route selection in a network
- Publication number 20070230369
- Publication date Oct 4, 2007
- Gary L. McAlpine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Traffic rate control in a network
- Publication number 20070153683
- Publication date Jul 5, 2007
- Gary L. McAlpine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for managing network congestion
- Publication number 20070058532
- Publication date Mar 15, 2007
- Manoj Wadekar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Congestion control in a network
- Publication number 20060104298
- Publication date May 18, 2006
- Gary L. McAlpine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Packet processing
- Publication number 20060072563
- Publication date Apr 6, 2006
- Greg J. Regnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Directional and priority based flow control mechanism between nodes
- Publication number 20060053117
- Publication date Mar 9, 2006
- Gary McAlpine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Virtual to physical address translation
- Publication number 20050144422
- Publication date Jun 30, 2005
- Gary L. McAlpine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for parallel processing of network data on a s...
- Publication number 20050138622
- Publication date Jun 23, 2005
- Gary L. McAlpine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Embedded transport acceleration architecture
- Publication number 20040103225
- Publication date May 27, 2004
- Intel Corporation
- Gary L. McAlpine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple-domain processing system using hierarchically orthogonal s...
- Publication number 20030086421
- Publication date May 8, 2003
- Oleg Awsienko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for a traffic optimizing multi-stage switch fa...
- Publication number 20020141427
- Publication date Oct 3, 2002
- Gary L. McAlpine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Gary L. McAlpine

Person

Patents Grantslast 30 patents

Directional and priority based flow control mechanism between nodes

Multiple-domain processing system using hierarchically orthogonal s...

Congestion control in a network

Directional and priority based flow control mechanism between nodes

Multiple-domain processing system using hierarchically orthogonal s...

Embedded transport acceleration architecture

Apparatus and method for parallel processing of network data on a s...

Hierarchical interrupt structure for event notification on multi-vi...

Adaptive transmit rate control scheduler

Patents Applicationslast 30 patents

DIRECTIONAL AND PRIORITY BASED FLOW CONTROL MECHANISM BETWEEN NODES

Multiple-domain processing system using hierarchically orthogonal s...

Route selection in a network

Traffic rate control in a network

System and method for managing network congestion

Congestion control in a network

Packet processing

Directional and priority based flow control mechanism between nodes

Virtual to physical address translation

Apparatus and method for parallel processing of network data on a s...

Embedded transport acceleration architecture

Multiple-domain processing system using hierarchically orthogonal s...

Method and apparatus for a traffic optimizing multi-stage switch fa...