Gary L. Taylor

Person

Windsor, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Latching pseudo-dual-port memory multiplexer
- Patent number 9,892,768
- Issue date Feb 13, 2018
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Gary L. Taylor
- G11 - INFORMATION STORAGE
Information Patent Grant
Deeply pipelined integrated memory built-in self-test (BIST) system...
- Patent number 8,837,243
- Issue date Sep 16, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Gary L. Taylor
- G11 - INFORMATION STORAGE
Information Patent Grant
Routing vias in a substrate from bypass capacitor pads
- Patent number 7,326,860
- Issue date Feb 5, 2008
- Hewlett-Packard Development Company, L.P.
- Jerimy Nelson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Source-synchronous receiver having a predetermined data receive time
- Patent number 7,127,536
- Issue date Oct 24, 2006
- Hewlett-Packard Development Company, L.P.
- Gary L. Taylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing vias in a substrate from bypass capacitor pads
- Patent number 7,075,185
- Issue date Jul 11, 2006
- Hewlett-Packard Development Company, L.P.
- Jerimy Nelson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit
- Patent number 7,019,367
- Issue date Mar 28, 2006
- Hewlett-Packard Development Company, L.P.
- Carson D. Henrion
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Divided clock generation
- Patent number 6,812,750
- Issue date Nov 2, 2004
- Hewlett-Packard Development Company, L.P.
- Carson Donahue Henrion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus adapter for synchronizing communications between two circuits r...
- Patent number 5,758,131
- Issue date May 26, 1998
- Hewlett-Packard Company
- Gary L. Taylor
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DEEPLY PIPELINED INTEGRATED MEMORY BUILT-IN SELF-TEST (BIST) SYSTEM...
- Publication number 20130223168
- Publication date Aug 29, 2013
- Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Gary L. Taylor
- G11 - INFORMATION STORAGE
Information Patent Application
LATCHING PSEUDO-DUAL-PORT MEMORY MULTIPLEXER
- Publication number 20130227223
- Publication date Aug 29, 2013
- Avago Technologies Enterprise IP(Singapore) Pte. L
- Gary L. Taylor
- G11 - INFORMATION STORAGE
Information Patent Application
Routing vias in a substrate from bypass capacitor pads
- Publication number 20060225916
- Publication date Oct 12, 2006
- Jerimy Nelson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Routing vias in a substrate from bypass capacitor pads
- Publication number 20060055049
- Publication date Mar 16, 2006
- Jerimy Nelson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Integrated circuit
- Publication number 20050051794
- Publication date Mar 10, 2005
- Carson D. Henrion
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Source-synchronous receiver having a predetermined data receive time
- Publication number 20040062323
- Publication date Apr 1, 2004
- Gary L. Taylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlled impedance driver receiving a combination binary and ther...
- Publication number 20020135406
- Publication date Sep 26, 2002
- KM Mozammel Hossain
- H03 - BASIC ELECTRONIC CIRCUITRY

Gary L. Taylor

Person

Patents Grantslast 30 patents

Latching pseudo-dual-port memory multiplexer

Deeply pipelined integrated memory built-in self-test (BIST) system...

Routing vias in a substrate from bypass capacitor pads

Source-synchronous receiver having a predetermined data receive time

Routing vias in a substrate from bypass capacitor pads

Integrated circuit

Divided clock generation

Bus adapter for synchronizing communications between two circuits r...

Patents Applicationslast 30 patents

DEEPLY PIPELINED INTEGRATED MEMORY BUILT-IN SELF-TEST (BIST) SYSTEM...

LATCHING PSEUDO-DUAL-PORT MEMORY MULTIPLEXER

Routing vias in a substrate from bypass capacitor pads

Routing vias in a substrate from bypass capacitor pads

Integrated circuit

Source-synchronous receiver having a predetermined data receive time

Controlled impedance driver receiving a combination binary and ther...