Gary L. Whisenhunt

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Interrupt priority management using partition-based priority blocki...
- Patent number 9,442,870
- Issue date Sep 13, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Bryan D. Marietta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor interrupt interface with interrupt partitioning and virtu...
- Patent number 9,436,626
- Issue date Sep 6, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Bryan D. Marietta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug instruction for execution by a first thread to generate a deb...
- Patent number 9,395,983
- Issue date Jul 19, 2016
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtualized instruction extensions for system partitioning
- Patent number 9,229,884
- Issue date Jan 5, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Bryan D. Marietta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processor for processing a decorated storage notify
- Patent number 9,213,665
- Issue date Dec 15, 2015
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtualized interrupt delay mechanism
- Patent number 9,152,587
- Issue date Oct 6, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Bryan D. Marietta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indicating disabled thread to other threads when contending instruc...
- Patent number 9,047,079
- Issue date Jun 2, 2015
- International Business Machines Corporation
- Becky Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread de-emphasis instruction for multithreaded processor
- Patent number 8,832,702
- Issue date Sep 9, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Klas M. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Permissions checking for data processing instructions
- Patent number 8,627,471
- Issue date Jan 7, 2014
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with hardware thread control logic indicating disable sta...
- Patent number 8,615,644
- Issue date Dec 24, 2013
- International Business Machines Corporation
- Becky Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Polling using reservation mechanism
- Patent number 8,539,485
- Issue date Sep 17, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Michael D. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Qualification of conditional debug instructions based on address
- Patent number 8,261,047
- Issue date Sep 4, 2012
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forward progress mechanism for a multithreaded processor
- Patent number 8,117,618
- Issue date Feb 14, 2012
- FREESCALE SEMICONDUCTOR, INC.
- David C. Holloway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable error actions for a cache in a data processing system
- Patent number 8,095,831
- Issue date Jan 10, 2012
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interprocessor message transmission via coherency-based interconnect
- Patent number 7,941,499
- Issue date May 10, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Becky G. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interrupt controller for accelerated interrupt handling in a data p...
- Patent number 7,849,247
- Issue date Dec 7, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Bryan D. Marietta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache locking device and methods thereof
- Patent number 7,827,360
- Issue date Nov 2, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Syed R. Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple address and arithmetic bit-mode data processing device and...
- Patent number 7,805,581
- Issue date Sep 28, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Michael D. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for data transfers across different address spaces
- Patent number 7,702,881
- Issue date Apr 20, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Becky G. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug instruction for use in a data processing system
- Patent number 7,689,815
- Issue date Mar 30, 2010
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction for conditionally yielding to a ready thread based on p...
- Patent number 7,584,344
- Issue date Sep 1, 2009
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor having a content addressable memory (CAM) device as...
- Patent number 6,792,502
- Issue date Sep 14, 2004
- FREESCALE SEMICONDUCTOR, INC.
- Mihir A. Pandya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Development interface for a data processor
- Patent number 6,145,122
- Issue date Nov 7, 2000
- Motorola, Inc.
- Gary Lynn Miller
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Interrupt Priority Management Using Partition-Based Priority Blocki...
- Publication number 20140047149
- Publication date Feb 13, 2014
- Bryan D. Marietta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor Interrupt Interface with Interrupt Partitioning and Virtu...
- Publication number 20140047150
- Publication date Feb 13, 2014
- Bryan D. Marietta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtualized Interrupt Delay Mechanism
- Publication number 20130326102
- Publication date Dec 5, 2013
- Bryan D. Marietta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtualized Instruction Extensions for System Partitioning
- Publication number 20130290585
- Publication date Oct 31, 2013
- Bryan D. Marietta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE...
- Publication number 20120185678
- Publication date Jul 19, 2012
- International Business Machines Corporation
- Becky Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE...
- Publication number 20110208949
- Publication date Aug 25, 2011
- International Business Machines Corporation
- Becky Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE ERROR ACTIONS FOR A CACHE IN A DATA PROCESSING SYSTEM
- Publication number 20100125750
- Publication date May 20, 2010
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSOR FOR PROCESSING A DECORATED STORAGE NOTIFY
- Publication number 20100106872
- Publication date Apr 29, 2010
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERMISSIONS CHECKING FOR DATA PROCESSING INSTRUCTIONS
- Publication number 20100107243
- Publication date Apr 29, 2010
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERRUPT ACKNOWLEDGMENT IN A DATA PROCESSING SYSTEM
- Publication number 20100095039
- Publication date Apr 15, 2010
- Bryan D. Marietta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG INSTRUCTION FOR USE IN A MULTI-THREADED DATA PROCESSING SYSTEM
- Publication number 20100049955
- Publication date Feb 25, 2010
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG INSTRUCTION FOR USE IN A MULTI-THREADED DATA PROCESSING SYSTEM
- Publication number 20100049956
- Publication date Feb 25, 2010
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUALIFICATION OF CONDITIONAL DEBUG INSTRUCTIONS BASED ON ADDRESS
- Publication number 20090235059
- Publication date Sep 17, 2009
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POLLING USING RESERVATION MECHANISM
- Publication number 20090132796
- Publication date May 21, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Michael D. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FORWARD PROGRESS MECHANISM FOR A MULTITHREADED PROCESSOR
- Publication number 20090100432
- Publication date Apr 16, 2009
- FREESCALE SEMICONDUCTOR, INC.
- David C. Holloway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG INSTRUCTION FOR USE IN A DATA PROCESSING SYSTEM
- Publication number 20090100254
- Publication date Apr 16, 2009
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE LOCKING DEVICE AND METHODS THEREOF
- Publication number 20090037666
- Publication date Feb 5, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Syed R. Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECIFICATION OF COHERENCE DOMAIN DURING ADDRESS TRANSLATION
- Publication number 20090019232
- Publication date Jan 15, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR
- Publication number 20080282251
- Publication date Nov 13, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Klas M. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERPROCESSOR MESSAGE TRANSMISSION VIA COHERENCY-BASED INTERCONNECT
- Publication number 20080222389
- Publication date Sep 11, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Becky G. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-MODE DATA PROCESSING DEVICE AND METHODS THEREOF
- Publication number 20080209182
- Publication date Aug 28, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Michael D. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR DATA TRANSFERS ACROSS DIFFERENT ADDRESS SPACES
- Publication number 20080183943
- Publication date Jul 31, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Becky G. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT HAVING A CONDITIONAL YIELD INSTRUCTION AND METHO...
- Publication number 20070260863
- Publication date Nov 8, 2007
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING

Gary L. Whisenhunt

Person

Patents Grantslast 30 patents

Interrupt priority management using partition-based priority blocki...

Processor interrupt interface with interrupt partitioning and virtu...

Debug instruction for execution by a first thread to generate a deb...

Virtualized instruction extensions for system partitioning

Data processor for processing a decorated storage notify

Virtualized interrupt delay mechanism

Indicating disabled thread to other threads when contending instruc...

Thread de-emphasis instruction for multithreaded processor

Permissions checking for data processing instructions

Processor with hardware thread control logic indicating disable sta...

Polling using reservation mechanism

Qualification of conditional debug instructions based on address

Forward progress mechanism for a multithreaded processor

Programmable error actions for a cache in a data processing system

Interprocessor message transmission via coherency-based interconnect

Interrupt controller for accelerated interrupt handling in a data p...

Cache locking device and methods thereof

Multiple address and arithmetic bit-mode data processing device and...

Method and system for data transfers across different address spaces

Debug instruction for use in a data processing system

Instruction for conditionally yielding to a ready thread based on p...

Microprocessor having a content addressable memory (CAM) device as...

Development interface for a data processor

Patents Applicationslast 30 patents

Interrupt Priority Management Using Partition-Based Priority Blocki...

Processor Interrupt Interface with Interrupt Partitioning and Virtu...

Virtualized Interrupt Delay Mechanism

Virtualized Instruction Extensions for System Partitioning

HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE...

HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE...

PROGRAMMABLE ERROR ACTIONS FOR A CACHE IN A DATA PROCESSING SYSTEM

DATA PROCESSOR FOR PROCESSING A DECORATED STORAGE NOTIFY

PERMISSIONS CHECKING FOR DATA PROCESSING INSTRUCTIONS

INTERRUPT ACKNOWLEDGMENT IN A DATA PROCESSING SYSTEM

DEBUG INSTRUCTION FOR USE IN A MULTI-THREADED DATA PROCESSING SYSTEM

DEBUG INSTRUCTION FOR USE IN A MULTI-THREADED DATA PROCESSING SYSTEM

QUALIFICATION OF CONDITIONAL DEBUG INSTRUCTIONS BASED ON ADDRESS

POLLING USING RESERVATION MECHANISM

FORWARD PROGRESS MECHANISM FOR A MULTITHREADED PROCESSOR

DEBUG INSTRUCTION FOR USE IN A DATA PROCESSING SYSTEM

CACHE LOCKING DEVICE AND METHODS THEREOF

SPECIFICATION OF COHERENCE DOMAIN DURING ADDRESS TRANSLATION

THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR

INTERPROCESSOR MESSAGE TRANSMISSION VIA COHERENCY-BASED INTERCONNECT

MULTI-MODE DATA PROCESSING DEVICE AND METHODS THEREOF

METHOD AND SYSTEM FOR DATA TRANSFERS ACROSS DIFFERENT ADDRESS SPACES

INTEGRATED CIRCUIT HAVING A CONDITIONAL YIELD INSTRUCTION AND METHO...