Gary Paul Powell

Person

Allentow, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Noise-shielding, switch-controlled load circuitry for oscillators a...
- Patent number 7,132,903
- Issue date Nov 7, 2006
- Lattice Semiconductor Corporation
- Phillip Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock generation
- Patent number 7,091,763
- Issue date Aug 15, 2006
- Lattice Semiconductor Corporation
- Phillip Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable lock detector and corrector
- Patent number 6,970,047
- Issue date Nov 29, 2005
- Lattice Semiconductor Corporation
- Phillip Johnson
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Signaling voltage range discriminator
- Patent number 6,124,732
- Issue date Sep 26, 2000
- Lucent Technologies, Inc.
- Zeljko Zilic
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Operating voltage adapting buffer
- Patent number 6,111,450
- Issue date Aug 29, 2000
- Lucent Technologies, Inc.
- Gary Paul Powell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Global signal distribution with reduced routing tracks in an FPGA
- Patent number 6,064,225
- Issue date May 16, 2000
- Lucent Technologies Inc.
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuration pin emulation circuit for a field programmable gate a...
- Patent number 5,862,365
- Issue date Jan 19, 1999
- Lucent Technologies Inc.
- Ronald T. Modo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for converting field-programmable gate array i...
- Patent number 5,526,278
- Issue date Jun 11, 1996
- AT&T Corp.
- Gary P. Powell
- G06 - COMPUTING CALCULATING COUNTING

Gary Paul Powell

Person

Patents Grantslast 30 patents

Noise-shielding, switch-controlled load circuitry for oscillators a...

Clock generation

Programmable lock detector and corrector

Signaling voltage range discriminator

Operating voltage adapting buffer

Global signal distribution with reduced routing tracks in an FPGA

Configuration pin emulation circuit for a field programmable gate a...

Method and apparatus for converting field-programmable gate array i...