Ge YANG

Person

Dublin, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Full adder cell with improved power efficiency
- Patent number 11,294,631
- Issue date Apr 5, 2022
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full adder cell with improved power efficiency
- Patent number 11,169,779
- Issue date Nov 9, 2021
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power flip-flop element with gated clock
- Patent number 10,931,266
- Issue date Feb 23, 2021
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mixed threshold flip-flop element to mitigate hold time penalty due...
- Patent number 10,181,842
- Issue date Jan 15, 2019
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient scan latch systems and methods
- Patent number 10,120,028
- Issue date Nov 6, 2018
- NVIDIA Corporation
- Ilyas Elkin
- G01 - MEASURING TESTING
Information Patent Grant
Mitigating external influences on long signal lines
- Patent number 9,842,631
- Issue date Dec 12, 2017
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM core cell design with write assist
- Patent number 9,542,992
- Issue date Jan 10, 2017
- NVIDIA Corporation
- Hwong-Kwo Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Low clocking power flip-flop
- Patent number 9,525,401
- Issue date Dec 20, 2016
- NVIDIA Corporation
- Xi Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power savings via selection of SRAM power source
- Patent number 9,484,115
- Issue date Nov 1, 2016
- NVIDIA Corporation
- Stephen Felix
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power master-slave flip-flop
- Patent number 9,438,213
- Issue date Sep 6, 2016
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient scan latch systems and methods
- Patent number 9,435,861
- Issue date Sep 6, 2016
- NVIDIA Corporation
- Ilyas Elkin
- G01 - MEASURING TESTING
Information Patent Grant
Low tau synchronizer flip-flop with dual loop feedback approach to...
- Patent number 9,219,480
- Issue date Dec 22, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip-flop circuit having a reduced hold time requirement for a scan...
- Patent number 9,110,141
- Issue date Aug 18, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING
Information Patent Grant
Low power master-slave flip-flop
- Patent number 9,071,233
- Issue date Jun 30, 2015
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power, single-rail level shifters employing power down signal f...
- Patent number 9,071,240
- Issue date Jun 30, 2015
- NVIDIA Corporation
- Hank Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Small area low power data retention flop
- Patent number 8,988,123
- Issue date Mar 24, 2015
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock gating latch, method of operation thereof and integrated circ...
- Patent number 8,890,573
- Issue date Nov 18, 2014
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual flip-flop circuit
- Patent number 8,866,528
- Issue date Oct 21, 2014
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING
Information Patent Grant
Dual-trigger low-energy flip-flop circuit
- Patent number 8,604,855
- Issue date Dec 10, 2013
- NVIDIA Corporation
- William J. Dally
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power single rail input voltage level shifter
- Patent number 7,839,170
- Issue date Nov 23, 2010
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power single-rail-input voltage level shifter
- Patent number 7,830,175
- Issue date Nov 9, 2010
- NVIDIA Corporation
- Hwong-Kwo Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-timed dynamic sense amplifier flop circuit apparatus and method
- Patent number 7,772,891
- Issue date Aug 10, 2010
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifter circuit to shift signals from a logic voltage to an i...
- Patent number 7,772,885
- Issue date Aug 10, 2010
- NVIDIA Corporation
- Hwong-Kwo Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Process variation tolerant sense amplifier flop design
- Patent number 7,768,320
- Issue date Aug 3, 2010
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Area efficient high performance memory cell
- Patent number 7,649,762
- Issue date Jan 19, 2010
- NVIDIA Corporation
- Hwong-Kwo Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sequentially-accessed 1R/1W double-pumped single port SRAM with sha...
- Patent number 7,643,330
- Issue date Jan 5, 2010
- NVIDIA Corporation
- Hwong-Kwo Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed single-ended memory read circuit
- Patent number 7,626,871
- Issue date Dec 1, 2009
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Active bit line charge keeper
- Patent number 7,626,878
- Issue date Dec 1, 2009
- NVIDIA Corporation
- Hwong-Kwo Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
2-write 3-read SRAM design using a 12-T storage cell
- Patent number 7,626,854
- Issue date Dec 1, 2009
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for preventing current leakage when a low volt...
- Patent number 7,583,126
- Issue date Sep 1, 2009
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY
- Publication number 20210124558
- Publication date Apr 29, 2021
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY
- Publication number 20210124559
- Publication date Apr 29, 2021
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT SCAN LATCH SYSTEMS AND METHODS
- Publication number 20170234927
- Publication date Aug 17, 2017
- NVIDIA Corporation
- Ilyas Elkin
- G01 - MEASURING TESTING
Information Patent Application
MIXED THRESHOLD FLIP-FLOP ELEMENT TO MITIGATE HOLD TIME PENALTY DUE...
- Publication number 20170141768
- Publication date May 18, 2017
- NVIDIA Corporation
- Ge YANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
POWER SAVINGS VIA SELECTION OF SRAM POWER SOURCE
- Publication number 20160336054
- Publication date Nov 17, 2016
- NVIDIA CORPORTION
- Stephen FELIX
- G11 - INFORMATION STORAGE
Information Patent Application
LOW CLOCKING POWER FLIP-FLOP
- Publication number 20160269002
- Publication date Sep 15, 2016
- NVIDIA Corporation
- Xi Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER FLIP-FLOP ELEMENT WITH GATED CLOCK
- Publication number 20160043706
- Publication date Feb 11, 2016
- NVIDIA Corporation
- Ilyas ELKIN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER MASTER-SLAVE FLIP-FLOP
- Publication number 20150263708
- Publication date Sep 17, 2015
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO...
- Publication number 20150222266
- Publication date Aug 6, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER MASTER-SLAVE FLIP-FLOP
- Publication number 20150028927
- Publication date Jan 29, 2015
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SRAM CORE CELL DESIGN WITH WRITE ASSIST
- Publication number 20140313817
- Publication date Oct 23, 2014
- NVIDIA Corporation
- Hwong-Kwo LIN
- G11 - INFORMATION STORAGE
Information Patent Application
MITIGATING EXTERNAL INFLUENCES ON LONG SIGNAL LINES
- Publication number 20140169108
- Publication date Jun 19, 2014
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Application
SMALL AREA LOW POWER DATA RETENTION FLOP
- Publication number 20140167828
- Publication date Jun 19, 2014
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL FLIP-FLOP CIRCUIT
- Publication number 20140125377
- Publication date May 8, 2014
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING
Information Patent Application
FLIP-FLOP CIRCUIT HAVING A REDUCED HOLD TIME REQUIREMENT FOR A SCAN...
- Publication number 20140129887
- Publication date May 8, 2014
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING
Information Patent Application
EFFICIENT SCAN LATCH SYSTEMS AND METHODS
- Publication number 20140122949
- Publication date May 1, 2014
- NVIDIA Corporation
- Ilyas Elkin
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER, SINGLE-RAIL LEVEL SHIFTERS EMPLOYING POWER DOWN SIGNAL F...
- Publication number 20140084984
- Publication date Mar 27, 2014
- NVIDIA Corporation
- Hank Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK GATING LATCH, METHOD OF OPERATION THEREOF AND INTEGRATED CIRC...
- Publication number 20140070847
- Publication date Mar 13, 2014
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT
- Publication number 20130278315
- Publication date Oct 24, 2013
- William J. Dally
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT
- Publication number 20120212271
- Publication date Aug 23, 2012
- William J. DALLY
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
GENERIC FLEXIBLE TIMER DESIGN
- Publication number 20090045847
- Publication date Feb 19, 2009
- Hwong-Kwo Lin
- G04 - HOROLOGY
Information Patent Application
APPARATUS AND METHOD FOR PREVENTING CURRENT LEAKAGE WHEN A LOW VOLT...
- Publication number 20080290935
- Publication date Nov 27, 2008
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Full adder cell with improved power efficiency

Full adder cell with improved power efficiency

Low power flip-flop element with gated clock

Mixed threshold flip-flop element to mitigate hold time penalty due...

Efficient scan latch systems and methods

Mitigating external influences on long signal lines

SRAM core cell design with write assist

Low clocking power flip-flop

Power savings via selection of SRAM power source

Low power master-slave flip-flop

Efficient scan latch systems and methods

Low tau synchronizer flip-flop with dual loop feedback approach to...

Flip-flop circuit having a reduced hold time requirement for a scan...

Low power master-slave flip-flop

Low power, single-rail level shifters employing power down signal f...

Small area low power data retention flop

Clock gating latch, method of operation thereof and integrated circ...

Dual flip-flop circuit

Dual-trigger low-energy flip-flop circuit

Low power single rail input voltage level shifter

Low power single-rail-input voltage level shifter

Self-timed dynamic sense amplifier flop circuit apparatus and method

Level shifter circuit to shift signals from a logic voltage to an i...

Process variation tolerant sense amplifier flop design

Area efficient high performance memory cell

Sequentially-accessed 1R/1W double-pumped single port SRAM with sha...

High-speed single-ended memory read circuit

Active bit line charge keeper

2-write 3-read SRAM design using a 12-T storage cell

Apparatus and method for preventing current leakage when a low volt...

Patents Applicationslast 30 patents

FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY

FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY

EFFICIENT SCAN LATCH SYSTEMS AND METHODS

MIXED THRESHOLD FLIP-FLOP ELEMENT TO MITIGATE HOLD TIME PENALTY DUE...

POWER SAVINGS VIA SELECTION OF SRAM POWER SOURCE

LOW CLOCKING POWER FLIP-FLOP

LOW POWER FLIP-FLOP ELEMENT WITH GATED CLOCK

LOW POWER MASTER-SLAVE FLIP-FLOP

LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO...

LOW POWER MASTER-SLAVE FLIP-FLOP

SRAM CORE CELL DESIGN WITH WRITE ASSIST

MITIGATING EXTERNAL INFLUENCES ON LONG SIGNAL LINES

SMALL AREA LOW POWER DATA RETENTION FLOP

DUAL FLIP-FLOP CIRCUIT

FLIP-FLOP CIRCUIT HAVING A REDUCED HOLD TIME REQUIREMENT FOR A SCAN...

EFFICIENT SCAN LATCH SYSTEMS AND METHODS

LOW POWER, SINGLE-RAIL LEVEL SHIFTERS EMPLOYING POWER DOWN SIGNAL F...

CLOCK GATING LATCH, METHOD OF OPERATION THEREOF AND INTEGRATED CIRC...

DUAL-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT

DUAL-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT

GENERIC FLEXIBLE TIMER DESIGN

APPARATUS AND METHOD FOR PREVENTING CURRENT LEAKAGE WHEN A LOW VOLT...