Gen Pei

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
CMOS circuit having a tensile stress layer overlying an NMOS transi...
- Patent number 9,373,548
- Issue date Jun 21, 2016
- Advanced Micro Devices, Inc.
- Gen Pei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-thin SOI CMOS with raised epitaxial source and drain and embe...
- Patent number 8,012,820
- Issue date Sep 6, 2011
- International Business Machines Corporation
- Amlan Majumdar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress enhanced MOS circuits
- Patent number 7,943,999
- Issue date May 17, 2011
- Global Foundries Inc.
- Gen Pei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Negative differential resistance diode and SRAM utilizing such device
- Patent number 7,816,767
- Issue date Oct 19, 2010
- Advanced Micro Devices, Inc.
- Gen Pei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Negative differential resistance diode and SRAM utilizing such device
- Patent number 7,508,050
- Issue date Mar 24, 2009
- Advanced Micro Devices, Inc.
- Gen Pei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress enhanced CMOS circuits and methods for their fabrication
- Patent number 7,442,601
- Issue date Oct 28, 2008
- Advanced Micro Devices, Inc.
- Gen Pei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating stress enhanced MOS circuits
- Patent number 7,439,120
- Issue date Oct 21, 2008
- Advanced Micro Devices, Inc.
- Gen Pei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating a stress enhanced MOS circuit
- Patent number 7,416,931
- Issue date Aug 26, 2008
- Advanced Micro Devices, Inc.
- Gen Pei
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBE...
- Publication number 20110165739
- Publication date Jul 7, 2011
- International Business Machines Corporation
- Amlan Majumdar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBE...
- Publication number 20090289305
- Publication date Nov 26, 2009
- International Business Machines Corporation
- Amlan Majumdar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NEGATIVE DIFFERENTIAL RESISTANCE DIODE AND SRAM UTILIZING SUCH DEVICE
- Publication number 20090146212
- Publication date Jun 11, 2009
- Advanced Micro Devices, Inc.
- Gen Pei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS ENHANCED CMOS CIRCUITS
- Publication number 20090008718
- Publication date Jan 8, 2009
- Advanced Micro Devices, Inc.
- Gen PEI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS ENHANCED MOS CIRCUITS
- Publication number 20090001476
- Publication date Jan 1, 2009
- Advanced Micro Devices, Inc.
- Gen PEI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBE...
- Publication number 20080217686
- Publication date Sep 11, 2008
- International Business Machines Corporation
- Amlan Majumdar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING A STRESS ENHANCED MOS CIRCUIT
- Publication number 20080124877
- Publication date May 29, 2008
- Gen Pei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS ENHANCED CMOS CIRCUITS AND METHODS FOR THEIR FABRICATION
- Publication number 20080122002
- Publication date May 29, 2008
- Gen Pei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS ENHANCED MOS CIRCUITS AND METHODS FOR THEIR FABRICATION
- Publication number 20080038886
- Publication date Feb 14, 2008
- Gen Pei
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

CMOS circuit having a tensile stress layer overlying an NMOS transi...

Ultra-thin SOI CMOS with raised epitaxial source and drain and embe...

Stress enhanced MOS circuits

Negative differential resistance diode and SRAM utilizing such device

Negative differential resistance diode and SRAM utilizing such device

Stress enhanced CMOS circuits and methods for their fabrication

Method for fabricating stress enhanced MOS circuits

Methods for fabricating a stress enhanced MOS circuit

Patents Applicationslast 30 patents

ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBE...

ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBE...

NEGATIVE DIFFERENTIAL RESISTANCE DIODE AND SRAM UTILIZING SUCH DEVICE

STRESS ENHANCED CMOS CIRCUITS

STRESS ENHANCED MOS CIRCUITS

ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBE...

METHODS FOR FABRICATING A STRESS ENHANCED MOS CIRCUIT

STRESS ENHANCED CMOS CIRCUITS AND METHODS FOR THEIR FABRICATION

STRESS ENHANCED MOS CIRCUITS AND METHODS FOR THEIR FABRICATION