George K. Celler

Person

Lawrenceville, NJ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Thin epitaxial silicon carbide wafer fabrication
- Patent number 9,761,493
- Issue date Sep 12, 2017
- Rutgers, The State University of New Jersey
- George K. Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrates for monolithic optical circuits and electronic circuits
- Patent number 8,299,485
- Issue date Oct 30, 2012
- Soitec
- George K. Celler
- G02 - OPTICS
Information Patent Grant
Oxidation after oxide dissolution
- Patent number 8,148,242
- Issue date Apr 3, 2012
- Soitec
- Oleg Kononchuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Relaxation of a strained layer using a molten layer
- Patent number 7,968,911
- Issue date Jun 28, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- George K Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a device wafer with recyclable support
- Patent number 7,956,436
- Issue date Jun 7, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- George K Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a device wafer with recyclable support
- Patent number 7,605,054
- Issue date Oct 20, 2009
- S.O.I. Tec Silicon on Insulator Technologies
- George K Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer with diamond layer
- Patent number 7,605,055
- Issue date Oct 20, 2009
- S.O.I. Tec Silicon on Insulator Technologies
- George K Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Relaxation of a strained layer using a molten layer
- Patent number 7,585,792
- Issue date Sep 8, 2009
- S.O.I. Tec Silicon on Insulator Technologies
- George K Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of increasing the grain size of polycrystalline materials by...
- Patent number 4,406,709
- Issue date Sep 27, 1983
- Bell Telephone Laboratories, Incorporated
- George K. Celler
- C30 - CRYSTAL GROWTH
Information Patent Grant
Metallization for integrated circuits
- Patent number 4,258,078
- Issue date Mar 24, 1981
- Bell Telephone Laboratories, Incorporated
- George K. Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of removing contaminating impurities from device areas in a...
- Patent number 4,249,962
- Issue date Feb 10, 1981
- Western Electric Company, Inc.
- George K. Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming self-guarded p-n junctions by epitaxial regrowth of amorpho...
- Patent number 4,240,843
- Issue date Dec 23, 1980
- Western Electric Company, Inc.
- George K. Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterned epitaxial regrowth using overlapping pulsed irradiation
- Patent number 4,234,358
- Issue date Nov 18, 1980
- Western Electric Company, Inc.
- George K. Celler
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
THIN EPITAXIAL SILICON CARBIDE WAFER FABRICATION
- Publication number 20150214040
- Publication date Jul 30, 2015
- Rutgers, The State University of New Jersey
- GEORGE K. CELLER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATES FOR MONOLITHIC OPTICAL CIRCUITS AND ELECTRONIC CIRCUITS
- Publication number 20100295083
- Publication date Nov 25, 2010
- George K. Celler
- G02 - OPTICS
Information Patent Application
OXIDATION AFTER OXIDE DISSOLUTION
- Publication number 20100283118
- Publication date Nov 11, 2010
- S.O.I.TEC SILICON ON INSULATION TECHNOLOGIES
- Oleg Kononchuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A DEVICE WAFER WITH RECYCLABLE SUPPORT
- Publication number 20090315140
- Publication date Dec 24, 2009
- S.O.I.Tec Silicon on Insulator Technologies
- George K. Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RELAXATION OF A STRAINED LAYER USING A MOLTEN LAYER
- Publication number 20090261344
- Publication date Oct 22, 2009
- S.O.I.Tec Silicon on Insulator Technologies
- George K. Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A DEVICE WAFER WITH RECYCLABLE SUPPORT
- Publication number 20080261377
- Publication date Oct 23, 2008
- George K. Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer with diamond layer
- Publication number 20060276003
- Publication date Dec 7, 2006
- George K. Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Relaxation of a strained layer using a molten layer
- Publication number 20060175608
- Publication date Aug 10, 2006
- George K. Celler
- H01 - BASIC ELECTRIC ELEMENTS

George K. Celler

Person

Patents Grantslast 30 patents

Thin epitaxial silicon carbide wafer fabrication

Substrates for monolithic optical circuits and electronic circuits

Oxidation after oxide dissolution

Relaxation of a strained layer using a molten layer

Method of forming a device wafer with recyclable support

Method of forming a device wafer with recyclable support

Wafer with diamond layer

Relaxation of a strained layer using a molten layer

Method of increasing the grain size of polycrystalline materials by...

Metallization for integrated circuits

Method of removing contaminating impurities from device areas in a...

Forming self-guarded p-n junctions by epitaxial regrowth of amorpho...

Patterned epitaxial regrowth using overlapping pulsed irradiation

Patents Applicationslast 30 patents

THIN EPITAXIAL SILICON CARBIDE WAFER FABRICATION

SUBSTRATES FOR MONOLITHIC OPTICAL CIRCUITS AND ELECTRONIC CIRCUITS

OXIDATION AFTER OXIDE DISSOLUTION

METHOD OF FORMING A DEVICE WAFER WITH RECYCLABLE SUPPORT

RELAXATION OF A STRAINED LAYER USING A MOLTEN LAYER

METHOD OF FORMING A DEVICE WAFER WITH RECYCLABLE SUPPORT

Wafer with diamond layer

Relaxation of a strained layer using a molten layer