George R. Leal

Person

Cedar Park, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Matrix lid heatspreader for flip chip package
- Patent number 9,640,469
- Issue date May 2, 2017
- NXP USA, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Matrix lid heatspreader for flip chip package
- Patent number 9,159,643
- Issue date Oct 13, 2015
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for singulating electronic components from a substrate
- Patent number 9,142,434
- Issue date Sep 22, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Wei Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Warp compensated electronic assemblies
- Patent number 9,107,303
- Issue date Aug 11, 2015
- FREESCALE SEMICONDUCTOR, INC.
- William H. Lytle
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods and structures for reducing stress on die assembly
- Patent number 8,970,026
- Issue date Mar 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recovery method for poor yield at integrated circuit die panelization
- Patent number 8,877,523
- Issue date Nov 4, 2014
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Warp compensated package and method
- Patent number 8,829,661
- Issue date Sep 9, 2014
- FREESCALE SEMICONDUCTOR, INC.
- William H. Lytle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fused buss for plating features on a semiconductor die
- Patent number 8,368,172
- Issue date Feb 5, 2013
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fused buss for plating features on a semiconductor die
- Patent number 8,349,666
- Issue date Jan 8, 2013
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a packaged semiconductor device
- Patent number 8,216,918
- Issue date Jul 10, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Zhiwei Gong
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Circuit device with at least partial packaging and method for forming
- Patent number 8,072,062
- Issue date Dec 6, 2011
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for controlling warpage in redistributed chip packaging panels
- Patent number 7,950,144
- Issue date May 31, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Lakshmi N. Ramanathan
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Methods and apparatus for a semiconductor device package with impro...
- Patent number 7,892,882
- Issue date Feb 22, 2011
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with a protected active die region and method...
- Patent number 7,579,219
- Issue date Aug 25, 2009
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming crack arrest features in embedded device build-up...
- Patent number 7,553,753
- Issue date Jun 30, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Jie-Hua Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fine pitch interconnect and method of making
- Patent number 7,528,069
- Issue date May 5, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Robert J. Wenzel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for thermal management in a multi-layer embed...
- Patent number 7,405,102
- Issue date Jul 29, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Tien Yu T. Lee
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Circuit device with at least partial packaging and method for forming
- Patent number 7,361,987
- Issue date Apr 22, 2008
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a bond pad and method therefor
- Patent number 7,271,013
- Issue date Sep 18, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Lois E. Yong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit device with at least partial packaging, exposed active surf...
- Patent number 6,921,975
- Issue date Jul 26, 2005
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a bond pad and method therefor
- Patent number 6,844,631
- Issue date Jan 18, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Lois E. Yong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit device with at least partial packaging and method for forming
- Patent number 6,838,776
- Issue date Jan 4, 2005
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Matrix Lid Heatspreader for Flip Chip Package
- Publication number 20160005682
- Publication date Jan 7, 2016
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRAMMABLE STITCH CHAINING OF DIE-LEVEL INTERCONNECTS FOR RELIABI...
- Publication number 20150332980
- Publication date Nov 19, 2015
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- G01 - MEASURING TESTING
Information Patent Application
WARP COMPENSATED ELECTRONIC ASSEMBLIES
- Publication number 20140369015
- Publication date Dec 18, 2014
- William H. Lytle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND STRUCTURES FOR REDUCING STRESS ON DIE ASSEMBLY
- Publication number 20140225268
- Publication date Aug 14, 2014
- GEORGE R. LEAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Matrix Lid Heatspreader for Flip Chip Package
- Publication number 20140077352
- Publication date Mar 20, 2014
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE
- Publication number 20130020674
- Publication date Jan 24, 2013
- GEORGE R. LEAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE
- Publication number 20130023091
- Publication date Jan 24, 2013
- GEORGE R. LEAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECOVERY METHOD FOR POOR YIELD AT INTEGRATED CIRCUIT DIE PANELIZATION
- Publication number 20120329212
- Publication date Dec 27, 2012
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE
- Publication number 20120021565
- Publication date Jan 26, 2012
- Zhiwei Gong
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD FOR SINGULATING ELECTRONIC COMPONENTS FROM A SUBSTRATE
- Publication number 20110217814
- Publication date Sep 8, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Wei Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF PACKAGING INTEGRATED CIRCUIT DIES WITH THERMAL DISSIPATIO...
- Publication number 20100148357
- Publication date Jun 17, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Liyu Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR CONTROLLING WARPAGE IN REDISTRIBUTED CHIP PACKAGING PANELS
- Publication number 20090271980
- Publication date Nov 5, 2009
- Lakshmi N. Ramanathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT DEVICE WITH AT LEAST PARTIAL PACKAGING AND METHOD FOR FORMING
- Publication number 20080142960
- Publication date Jun 19, 2008
- FREESCALE SEMICONDUCTOR, INC.
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING CRACK ARREST FEATURES IN EMBEDDED DEVICE BUILD-UP...
- Publication number 20080057696
- Publication date Mar 6, 2008
- Jie-Hua Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and apparatus for a semiconductor device package with impro...
- Publication number 20070284704
- Publication date Dec 13, 2007
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and apparatus for thermal management in a multi-layer embed...
- Publication number 20070284711
- Publication date Dec 13, 2007
- Tien Yu T. Lee
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Warp compensated package and method
- Publication number 20070210427
- Publication date Sep 13, 2007
- William H. Lytle
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Perforated embedded plane package and method
- Publication number 20070212813
- Publication date Sep 13, 2007
- Owen R. Fay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fine pitch interconnect and method of making
- Publication number 20070102828
- Publication date May 10, 2007
- Robert J. Wenzel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with a protected active die region and method...
- Publication number 20060192301
- Publication date Aug 31, 2006
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Circuit device with at least partial packaging and method for forming
- Publication number 20060012036
- Publication date Jan 19, 2006
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with a protected active die region and method...
- Publication number 20050242425
- Publication date Nov 3, 2005
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having a bond pad and method therefor
- Publication number 20050098903
- Publication date May 12, 2005
- Loise E. Yong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Circuit device with at least partial packaging and method for forming
- Publication number 20040207077
- Publication date Oct 21, 2004
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Circuit device with at least partial packaging and method for forming
- Publication number 20040207068
- Publication date Oct 21, 2004
- George R. Leal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having a bond pad and method therefor
- Publication number 20030173667
- Publication date Sep 18, 2003
- Lois E. Yong
- H01 - BASIC ELECTRIC ELEMENTS

George R. Leal

Person

Patents Grantslast 30 patents

Matrix lid heatspreader for flip chip package

Matrix lid heatspreader for flip chip package

Method for singulating electronic components from a substrate

Warp compensated electronic assemblies

Methods and structures for reducing stress on die assembly

Recovery method for poor yield at integrated circuit die panelization

Warp compensated package and method

Fused buss for plating features on a semiconductor die

Fused buss for plating features on a semiconductor die

Method of forming a packaged semiconductor device

Circuit device with at least partial packaging and method for forming

Method for controlling warpage in redistributed chip packaging panels

Methods and apparatus for a semiconductor device package with impro...

Semiconductor device with a protected active die region and method...

Method of forming crack arrest features in embedded device build-up...

Fine pitch interconnect and method of making

Methods and apparatus for thermal management in a multi-layer embed...

Circuit device with at least partial packaging and method for forming

Semiconductor device having a bond pad and method therefor

Circuit device with at least partial packaging, exposed active surf...

Semiconductor device having a bond pad and method therefor

Circuit device with at least partial packaging and method for forming

Patents Applicationslast 30 patents

Matrix Lid Heatspreader for Flip Chip Package

PROGRAMMABLE STITCH CHAINING OF DIE-LEVEL INTERCONNECTS FOR RELIABI...

WARP COMPENSATED ELECTRONIC ASSEMBLIES

METHODS AND STRUCTURES FOR REDUCING STRESS ON DIE ASSEMBLY

Matrix Lid Heatspreader for Flip Chip Package

FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE

FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE

RECOVERY METHOD FOR POOR YIELD AT INTEGRATED CIRCUIT DIE PANELIZATION

METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE

METHOD FOR SINGULATING ELECTRONIC COMPONENTS FROM A SUBSTRATE

METHOD OF PACKAGING INTEGRATED CIRCUIT DIES WITH THERMAL DISSIPATIO...

METHOD FOR CONTROLLING WARPAGE IN REDISTRIBUTED CHIP PACKAGING PANELS

CIRCUIT DEVICE WITH AT LEAST PARTIAL PACKAGING AND METHOD FOR FORMING

METHOD OF FORMING CRACK ARREST FEATURES IN EMBEDDED DEVICE BUILD-UP...

Methods and apparatus for a semiconductor device package with impro...

Methods and apparatus for thermal management in a multi-layer embed...

Warp compensated package and method

Perforated embedded plane package and method

Fine pitch interconnect and method of making

Semiconductor device with a protected active die region and method...

Circuit device with at least partial packaging and method for forming

Semiconductor device with a protected active die region and method...

Semiconductor device having a bond pad and method therefor

Circuit device with at least partial packaging and method for forming

Circuit device with at least partial packaging and method for forming

Semiconductor device having a bond pad and method therefor