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George S. Taylor
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Menlo Park, CA, US
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last 30 patents
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Patent Grant
Software invalidation in a multiple level, multiple cache system
Patent number
5,699,551
Issue date
Dec 16, 1997
Silicon Graphics, Inc.
George S. Taylor
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Rescheduling conflicting issued instructions by delaying one confli...
Patent number
5,555,384
Issue date
Sep 10, 1996
Silicon Graphics, Inc.
David B. Roberts
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Cache memory system employing virtual address primary instruction a...
Patent number
5,542,062
Issue date
Jul 30, 1996
Silicon Graphics, Inc.
George S. Taylor
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Two-level cache memory system
Patent number
5,307,477
Issue date
Apr 26, 1994
MIPS Computer Systems, Inc.
George S. Taylor
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Two-level translation look-aside buffer using partial addresses for...
Patent number
5,226,133
Issue date
Jul 6, 1993
Silicon Graphics, Inc.
George S. Taylor
G06 - COMPUTING CALCULATING COUNTING