Gerhard Enders

Person

Olching, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Back gate in select transistor for eDRAM
- Patent number 9,472,469
- Issue date Oct 18, 2016
- Soitec
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sense amplifier with dual gate precharge and decode transistors
- Patent number 9,251,871
- Issue date Feb 2, 2016
- SOITEC
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory having staggered sense amplifiers associated w...
- Patent number 9,159,400
- Issue date Oct 13, 2015
- Soitec
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Grant
Fully depleted SOI device with buried doped layer
- Patent number 8,492,844
- Issue date Jul 23, 2013
- Soitec
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structure for semiconductor devices
- Patent number 8,138,538
- Issue date Mar 20, 2012
- Qimonda AG
- Hans-Peter Moll
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM memory with vertically arranged selection transistors
- Patent number 7,372,093
- Issue date May 13, 2008
- Infineon Technologies AG
- Michael Sommer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM memory having vertically arranged selection transistors
- Patent number 7,335,936
- Issue date Feb 26, 2008
- Infineon Technologies AG
- Michael Sommer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried strap contact for a storage capacitor and method for fabrica...
- Patent number 7,163,857
- Issue date Jan 16, 2007
- Infineon Technologies AG
- Peter Voigt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for processing a substrate to form a structure
- Patent number 7,109,091
- Issue date Sep 19, 2006
- Infineon Technologies AG
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a gate structure of a FET and gate structure...
- Patent number 7,081,392
- Issue date Jul 25, 2006
- Infineon Technologies AG
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor gate structure and method for fabricating a semicondu...
- Patent number 7,045,422
- Issue date May 16, 2006
- Infineon Technologies AG
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical transistor, and a method for producing a vertical transistor
- Patent number 7,034,358
- Issue date Apr 25, 2006
- Infineon Technologies AG
- Dietrich Bonart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-effect transistor
- Patent number 7,009,263
- Issue date Mar 7, 2006
- Infineon Technologies AG
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated semiconductor memory with a selection transistor formed...
- Patent number 6,992,345
- Issue date Jan 31, 2006
- Infineon Technologies, AG
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM memory cell and memory cell array with fast read/write access
- Patent number 6,979,853
- Issue date Dec 27, 2005
- Infineon Technologies AG
- Michael Sommer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dram cell and space-optimized memory array
- Patent number 6,876,025
- Issue date Apr 5, 2005
- Infineon Technologies AG
- Michael Sommer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor memory device
- Patent number 6,858,492
- Issue date Feb 22, 2005
- Infineon Technologies AG
- Rainer Bruchhaus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a vertical transistor, and semiconductor mem...
- Patent number 6,838,335
- Issue date Jan 4, 2005
- Infineon Technologies AG
- Dietrich Bonart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench cell for a DRAM cell array
- Patent number 6,822,281
- Issue date Nov 23, 2004
- Infineon Technologies AG
- Peter Voigt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor memory device
- Patent number 6,818,503
- Issue date Nov 16, 2004
- Infineon Technologies AG
- Rainer Bruchhaus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a buried strap contact in a memory cell
- Patent number 6,797,562
- Issue date Sep 28, 2004
- Infineon Technologies AG
- Dietrich Bonart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor memory device
- Patent number 6,773,986
- Issue date Aug 10, 2004
- Infineon Technologies AG
- Rainer Bruchhaus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory with vertical selection transistor
- Patent number 6,770,928
- Issue date Aug 3, 2004
- Infineon Technologies AG
- Michael Sommer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FeRAM memory and method for manufacturing it
- Patent number 6,704,219
- Issue date Mar 9, 2004
- Infineon Technologies AG
- Rainer Bruchhaus
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
BACK GATE IN SELECT TRANSISTOR FOR EDRAM
- Publication number 20150357333
- Publication date Dec 10, 2015
- SOITEC
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SENSE AMPLIFIER WITH DUAL GATE PRECHARGE AND DECODE TRANSISTORS
- Publication number 20140321225
- Publication date Oct 30, 2014
- SOITEC
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED W...
- Publication number 20120243360
- Publication date Sep 27, 2012
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Application
FULLY DEPLETED SOI DEVICE WITH BURIED DOPED LAYER
- Publication number 20120181609
- Publication date Jul 19, 2012
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES
- Publication number 20100090264
- Publication date Apr 15, 2010
- QIMONDA AG
- Hans-Peter Moll
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor memory cell array having self-aligned recessed gate M...
- Publication number 20070040202
- Publication date Feb 22, 2007
- Infineon Technologies AG
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried strap contact for a storage capacitor and method for fabrica...
- Publication number 20070002691
- Publication date Jan 4, 2007
- Peter Voigt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for producing a vertical transistor
- Publication number 20060148178
- Publication date Jul 6, 2006
- Infineon Technologies AG
- Dietrich Bonart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating a gate structure of a FET and gate structure...
- Publication number 20050085043
- Publication date Apr 21, 2005
- Infineon Technologies AG
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM memory with vertically arranged selection transistors
- Publication number 20050056873
- Publication date Mar 17, 2005
- Michael Sommer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried strap contact for a storage capacitor and method for fabrica...
- Publication number 20050026359
- Publication date Feb 3, 2005
- Infineon Technologies AG
- Peter Voigt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor gate structure and method for fabricating a semicondu...
- Publication number 20040262697
- Publication date Dec 30, 2004
- INFINEON TECHNOLOGIES
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Field-effect transistor
- Publication number 20040245576
- Publication date Dec 9, 2004
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM memory having vertically arranged selection transistors
- Publication number 20040197989
- Publication date Oct 7, 2004
- Michael Sommer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated semiconductor memory with a selection transistor formed...
- Publication number 20040136227
- Publication date Jul 15, 2004
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing a buried strap contact in a memory cell
- Publication number 20040048436
- Publication date Mar 11, 2004
- Dietrich Bonart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating a vertical transistor, and semiconductor mem...
- Publication number 20040021163
- Publication date Feb 5, 2004
- Dietrich Bonart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM cell and space-optimized memory array
- Publication number 20040007726
- Publication date Jan 15, 2004
- Michael Sommer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Vertical transistor, and a method for producing a vertical transistor
- Publication number 20040005762
- Publication date Jan 8, 2004
- Dietrich Bonart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM memory cell and memory cell array with fast read/write access
- Publication number 20040004891
- Publication date Jan 8, 2004
- Michael Sommer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Trench cell for a DRAM cell array
- Publication number 20030178662
- Publication date Sep 25, 2003
- Peter Voigt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor memory with vertical selection transistor
- Publication number 20030161201
- Publication date Aug 28, 2003
- Michael Sommer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for processing a substrate to form a structure
- Publication number 20030129837
- Publication date Jul 10, 2003
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating a semiconductor memory device
- Publication number 20030129796
- Publication date Jul 10, 2003
- Rainer Bruchhaus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating a semiconductor memory device
- Publication number 20030060002
- Publication date Mar 27, 2003
- Rainer Bruchhaus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating a semiconductor memory device
- Publication number 20030058700
- Publication date Mar 27, 2003
- Rainer Bruchhaus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FeRAM memory and method for manufacturing it
- Publication number 20030053346
- Publication date Mar 20, 2003
- Rainer Bruchhaus
- H01 - BASIC ELECTRIC ELEMENTS

Gerhard Enders

Person

Patents Grantslast 30 patents

Back gate in select transistor for eDRAM

Sense amplifier with dual gate precharge and decode transistors

Semiconductor memory having staggered sense amplifiers associated w...

Fully depleted SOI device with buried doped layer

Interconnect structure for semiconductor devices

DRAM memory with vertically arranged selection transistors

DRAM memory having vertically arranged selection transistors

Buried strap contact for a storage capacitor and method for fabrica...

Method for processing a substrate to form a structure

Method for fabricating a gate structure of a FET and gate structure...

Semiconductor gate structure and method for fabricating a semicondu...

Vertical transistor, and a method for producing a vertical transistor

Field-effect transistor

Integrated semiconductor memory with a selection transistor formed...

DRAM memory cell and memory cell array with fast read/write access

Dram cell and space-optimized memory array

Method for fabricating a semiconductor memory device

Method for fabricating a vertical transistor, and semiconductor mem...

Trench cell for a DRAM cell array

Method for fabricating a semiconductor memory device

Method for manufacturing a buried strap contact in a memory cell

Method for fabricating a semiconductor memory device

Semiconductor memory with vertical selection transistor

FeRAM memory and method for manufacturing it

Patents Applicationslast 30 patents

BACK GATE IN SELECT TRANSISTOR FOR EDRAM

SENSE AMPLIFIER WITH DUAL GATE PRECHARGE AND DECODE TRANSISTORS

SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED W...

FULLY DEPLETED SOI DEVICE WITH BURIED DOPED LAYER

INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES

Semiconductor memory cell array having self-aligned recessed gate M...

Buried strap contact for a storage capacitor and method for fabrica...

Method for producing a vertical transistor

Method for fabricating a gate structure of a FET and gate structure...

DRAM memory with vertically arranged selection transistors

Buried strap contact for a storage capacitor and method for fabrica...

Semiconductor gate structure and method for fabricating a semicondu...

Field-effect transistor

DRAM memory having vertically arranged selection transistors

Integrated semiconductor memory with a selection transistor formed...

Method for manufacturing a buried strap contact in a memory cell

Method for fabricating a vertical transistor, and semiconductor mem...

DRAM cell and space-optimized memory array

Vertical transistor, and a method for producing a vertical transistor

DRAM memory cell and memory cell array with fast read/write access

Trench cell for a DRAM cell array

Semiconductor memory with vertical selection transistor

Method for processing a substrate to form a structure

Method for fabricating a semiconductor memory device

Method for fabricating a semiconductor memory device

Method for fabricating a semiconductor memory device

FeRAM memory and method for manufacturing it