Gerrit J. Leusink

Person

Rexford, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for filling recessed features in semiconductor devices with...
- Patent number 12,237,216
- Issue date Feb 25, 2025
- Tokyo Electron Limited
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System for backside deposition of a substrate
- Patent number 11,908,728
- Issue date Feb 20, 2024
- Tokyo Electron Limited
- Ronald Nasman
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Semiconductor processing systems with in-situ electrical bias
- Patent number 11,894,240
- Issue date Feb 6, 2024
- Tokyo Electron Limited
- David Hurley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for filling recessed features in semiconductor devices with...
- Patent number 11,621,190
- Issue date Apr 4, 2023
- Tokyo Electron Limited
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor apparatus having stacked gates and method of manufact...
- Patent number 11,444,082
- Issue date Sep 13, 2022
- Tokyo Electron Limited
- Jeffrey Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming and using stress-tuned silicon oxide films in se...
- Patent number 11,443,953
- Issue date Sep 13, 2022
- Tokyo Electron Limited
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Area selective deposition for cap layer formation in advanced contacts
- Patent number 11,170,992
- Issue date Nov 9, 2021
- Tokyo Electron Limited
- Kandabara Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for filling recessed features in semiconductor devices with...
- Patent number 11,024,535
- Issue date Jun 1, 2021
- Tokyo Electron Limited
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structure and method of forming the same
- Patent number 10,923,392
- Issue date Feb 16, 2021
- Tokyo Electron Limited
- Soo Doo Chae
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a nanowire device
- Patent number 10,847,424
- Issue date Nov 24, 2020
- Tokyo Electron Limited
- Kandabara Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor apparatus having stacked gates and method of manufact...
- Patent number 10,833,078
- Issue date Nov 10, 2020
- Tokyo Electron Limited
- Jeffrey Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ruthenium metal feature fill for interconnects
- Patent number 10,700,009
- Issue date Jun 30, 2020
- Tokyo Electron Limited
- Kai-Hung Yu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of integrated circuit fabrication with dual metal power rail
- Patent number 10,580,691
- Issue date Mar 3, 2020
- Tokyo Electron Limited
- Soo Doo Chae
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structure and method of forming the same
- Patent number 10,541,174
- Issue date Jan 21, 2020
- Tokyo Electron Limited
- Soo Doo Chae
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of selective vertical growth of a dielectric material on a d...
- Patent number 10,453,681
- Issue date Oct 22, 2019
- Tokyo Electron Limited
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Processing system for electromagnetic wave treatment of a substrate...
- Patent number 10,426,001
- Issue date Sep 24, 2019
- Tokyo Electron Limited
- Ronald Nasman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of filling retrograde recessed features
- Patent number 10,410,861
- Issue date Sep 10, 2019
- Tokyo Electron Limited
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective deposition with surface treatment
- Patent number 10,378,105
- Issue date Aug 13, 2019
- Tokyo Electron Limited
- Kai-Hung Yu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Wrap-around contact integration scheme
- Patent number 10,217,670
- Issue date Feb 26, 2019
- Tokyo Electron Limited
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration of a self-forming barrier layer and a ruthenium metal l...
- Patent number 10,157,784
- Issue date Dec 18, 2018
- Tokyo Electron Limited
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective metal oxide deposition using a self-assembled monolayer s...
- Patent number 10,068,764
- Issue date Sep 4, 2018
- Tokyo Electron Limited
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ruthenium metal feature fill for interconnects
- Patent number 10,056,328
- Issue date Aug 21, 2018
- Tokyo Electron Limited
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective bottom-up metal feature filling for interconnects
- Patent number 10,014,213
- Issue date Jul 3, 2018
- Tokyo Electron Limited
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of corner rounding and trimming of nanowires by microwave pl...
- Patent number 10,008,564
- Issue date Jun 26, 2018
- Tokyo Electron Limited
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate tuning system and method using optical projection
- Patent number 9,735,067
- Issue date Aug 15, 2017
- Tokyo Electron Limited
- Anton J. deVilliers
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Ruthenium metal feature fill for interconnects
- Patent number 9,711,449
- Issue date Jul 18, 2017
- Tokyo Electron Limited
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for treating a substrate by optical projection of a correct...
- Patent number 9,646,898
- Issue date May 9, 2017
- Tokyo Electron Limited
- Anton J. deVilliers
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of forming conformal metal silicide films
- Patent number 8,785,310
- Issue date Jul 22, 2014
- Tokyo Electron Limited
- Toshio Hasegawa
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Semiconductor device containing a buried threshold voltage adjustme...
- Patent number 8,334,183
- Issue date Dec 18, 2012
- Tokyo Electron Limited
- Robert D. Clark
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for depositing a layer from light-induced vaporiz...
- Patent number 8,197,898
- Issue date Jun 12, 2012
- Tokyo Electron Limited
- Gerrit J. Leusink
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Patents Applicationslast 30 patents

Information Patent Application
2-DIMENSIONAL MATERIALS AS BARRIER LAYERS IN METALLIZATION OF SEMIC...
- Publication number 20240387371
- Publication date Nov 21, 2024
- TOKYO ELECTRON LIMITED
- Kandabara Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Processing Using a Two-Dimensional Polymer
- Publication number 20240363333
- Publication date Oct 31, 2024
- TOKYO ELECTRON LIMITED
- Kandabara Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR BACKSIDE DEPOSITION OF A SUBSTRATE
- Publication number 20240194516
- Publication date Jun 13, 2024
- TOKYO ELECTRON LIMITED
- Ronald Nasman
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
THERMAL ETCHING OF RUTHENIUM
- Publication number 20240153781
- Publication date May 9, 2024
- TOKYO ELECTRON LIMITED
- Hisashi Higuchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal Hard Mask Integration
- Publication number 20230260801
- Publication date Aug 17, 2023
- TOKYO ELECTRON LIMITED
- Angelique Raley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER BONDING METHOD USING SELECTIVE DEPOSITION AND SURFACE TREATMENT
- Publication number 20230075263
- Publication date Mar 9, 2023
- TOKYO ELECTRON LIMITED
- Soo Doo Chae
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Conductive Superlattice Structures and Methods of Forming the Same
- Publication number 20230051311
- Publication date Feb 16, 2023
- TOKYO ELECTRON LIMITED
- Hiroaki Niimi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE FILM FORMATION USING A SELF-ASSEMBLED MONOLAYER
- Publication number 20230009688
- Publication date Jan 12, 2023
- TOKYO ELECTRON LIMITED
- Dina H. Triyoso
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH...
- Publication number 20220301930
- Publication date Sep 22, 2022
- TOKYO ELECTRON LIMITED
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH...
- Publication number 20220139776
- Publication date May 5, 2022
- TOKYO ELECTRON LIMITED
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PROCESSING SYSTEMS WITH IN-SITU ELECTRICAL BIAS
- Publication number 20210313189
- Publication date Oct 7, 2021
- TOKYO ELECTRON LIMITED
- David Hurley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH...
- Publication number 20210287936
- Publication date Sep 16, 2021
- TOKYO ELECTRON LIMITED
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR APPARATUS HAVING STACKED GATES AND METHOD OF MANUFACT...
- Publication number 20210028169
- Publication date Jan 28, 2021
- TOKYO ELECTRON LIMITED
- Jeffrey SMITH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING AND USING STRESS-TUNED SILICON OXIDE FILMS IN SE...
- Publication number 20200152473
- Publication date May 14, 2020
- TOKYO ELECTRON LIMITED
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH...
- Publication number 20200118871
- Publication date Apr 16, 2020
- TOKYO ELECTRON LIMITED
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME
- Publication number 20200006129
- Publication date Jan 2, 2020
- TOKYO ELECTRON LIMITED
- Soo Doo CHAE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A NANOWIRE DEVICE
- Publication number 20190393097
- Publication date Dec 26, 2019
- TOKYO ELECTRON LIMITED
- Kandabara Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AREA SELECTIVE DEPOSITION FOR CAP LAYER FORMATION IN ADVANCED CONTACTS
- Publication number 20190333763
- Publication date Oct 31, 2019
- TOKYO ELECTRON LIMITED
- Kandabara Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR APPARATUS HAVING STACKED GATES AND METHOD OF MANUFACT...
- Publication number 20190172828
- Publication date Jun 6, 2019
- TOKYO ELECTRON LIMITED
- Jeffrey SMITH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RUTHENIUM METAL FEATURE FILL FOR INTERCONNECTS
- Publication number 20190103363
- Publication date Apr 4, 2019
- TOKYO ELECTRON LIMITED
- Kai-Hung Yu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
SYSTEM AND METHOD FOR BACKSIDE DEPOSITION OF A SUBSTRATE
- Publication number 20190035646
- Publication date Jan 31, 2019
- TOKYO ELECTRON LIMITED
- Ronald Nasman
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
METHOD OF INTEGRATED CIRCUIT FABRICATION WITH DUAL METAL POWER RAIL
- Publication number 20180350665
- Publication date Dec 6, 2018
- TOKYO ELECTRON LIMITED
- Soo Doo Chae
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF SELECTIVE VERTICAL GROWTH OF A DIELECTRIC MATERIAL ON A D...
- Publication number 20180301335
- Publication date Oct 18, 2018
- TOKYO ELECTRON LIMITED
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FILLING RETROGRADE RECESSED FEATURES
- Publication number 20180261450
- Publication date Sep 13, 2018
- TOKYO ELECTRON LIMITED
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME
- Publication number 20180211870
- Publication date Jul 26, 2018
- Soo Doo CHAE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE METAL OXIDE DEPOSITION USING A SELF-ASSEMBLED MONOLAYER S...
- Publication number 20180076027
- Publication date Mar 15, 2018
- TOKYO ELECTRON LIMITED
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WRAP-AROUND CONTACT INTEGRATION SCHEME
- Publication number 20180068899
- Publication date Mar 8, 2018
- TOKYO ELECTRON LIMITED
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF METAL FILLING RECESSED FEATURES IN A SUBSTRATE
- Publication number 20180053688
- Publication date Feb 22, 2018
- TOKYO ELECTRON LIMITED
- Kai-Hung Yu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
SELECTIVE DEPOSITION WITH SURFACE TREATMENT
- Publication number 20170342553
- Publication date Nov 30, 2017
- TOKYO ELECTRON LIMITED
- Kai-Hung Yu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
RUTHENIUM METAL FEATURE FILL FOR INTERCONNECTS
- Publication number 20170317022
- Publication date Nov 2, 2017
- TOKYO ELECTRON LIMITED
- Kai-Hung Yu
- H01 - BASIC ELECTRIC ELEMENTS

Gerrit J. Leusink

Person

Patents Grantslast 30 patents

Method for filling recessed features in semiconductor devices with...

System for backside deposition of a substrate

Semiconductor processing systems with in-situ electrical bias

Method for filling recessed features in semiconductor devices with...

Semiconductor apparatus having stacked gates and method of manufact...

Method for forming and using stress-tuned silicon oxide films in se...

Area selective deposition for cap layer formation in advanced contacts

Method for filling recessed features in semiconductor devices with...

Interconnect structure and method of forming the same

Method for forming a nanowire device

Semiconductor apparatus having stacked gates and method of manufact...

Ruthenium metal feature fill for interconnects

Method of integrated circuit fabrication with dual metal power rail

Interconnect structure and method of forming the same

Method of selective vertical growth of a dielectric material on a d...

Processing system for electromagnetic wave treatment of a substrate...

Method of filling retrograde recessed features

Selective deposition with surface treatment

Wrap-around contact integration scheme

Integration of a self-forming barrier layer and a ruthenium metal l...

Selective metal oxide deposition using a self-assembled monolayer s...

Ruthenium metal feature fill for interconnects

Selective bottom-up metal feature filling for interconnects

Method of corner rounding and trimming of nanowires by microwave pl...

Substrate tuning system and method using optical projection

Ruthenium metal feature fill for interconnects

Methods for treating a substrate by optical projection of a correct...

Method of forming conformal metal silicide films

Semiconductor device containing a buried threshold voltage adjustme...

Method and system for depositing a layer from light-induced vaporiz...

Patents Applicationslast 30 patents

2-DIMENSIONAL MATERIALS AS BARRIER LAYERS IN METALLIZATION OF SEMIC...

Semiconductor Processing Using a Two-Dimensional Polymer

SYSTEM AND METHOD FOR BACKSIDE DEPOSITION OF A SUBSTRATE

THERMAL ETCHING OF RUTHENIUM

Metal Hard Mask Integration

WAFER BONDING METHOD USING SELECTIVE DEPOSITION AND SURFACE TREATMENT

Conductive Superlattice Structures and Methods of Forming the Same

SELECTIVE FILM FORMATION USING A SELF-ASSEMBLED MONOLAYER

METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH...

METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH...

SEMICONDUCTOR PROCESSING SYSTEMS WITH IN-SITU ELECTRICAL BIAS

METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH...

SEMICONDUCTOR APPARATUS HAVING STACKED GATES AND METHOD OF MANUFACT...

METHOD FOR FORMING AND USING STRESS-TUNED SILICON OXIDE FILMS IN SE...

METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH...

INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

METHOD FOR FORMING A NANOWIRE DEVICE

AREA SELECTIVE DEPOSITION FOR CAP LAYER FORMATION IN ADVANCED CONTACTS

SEMICONDUCTOR APPARATUS HAVING STACKED GATES AND METHOD OF MANUFACT...

RUTHENIUM METAL FEATURE FILL FOR INTERCONNECTS

SYSTEM AND METHOD FOR BACKSIDE DEPOSITION OF A SUBSTRATE

METHOD OF INTEGRATED CIRCUIT FABRICATION WITH DUAL METAL POWER RAIL

METHOD OF SELECTIVE VERTICAL GROWTH OF A DIELECTRIC MATERIAL ON A D...

METHOD OF FILLING RETROGRADE RECESSED FEATURES

INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

SELECTIVE METAL OXIDE DEPOSITION USING A SELF-ASSEMBLED MONOLAYER S...

WRAP-AROUND CONTACT INTEGRATION SCHEME

METHOD OF METAL FILLING RECESSED FEATURES IN A SUBSTRATE

SELECTIVE DEPOSITION WITH SURFACE TREATMENT

RUTHENIUM METAL FEATURE FILL FOR INTERCONNECTS