Gianfranco Ferrante

Person

Naples, IT

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic updates to logical-to-physical address translation table bi...
- Patent number 11,928,063
- Issue date Mar 12, 2024
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for page line filler data
- Patent number 11,768,627
- Issue date Sep 26, 2023
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for page line filler data
- Patent number 11,556,275
- Issue date Jan 17, 2023
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilevel addressing
- Patent number 11,461,228
- Issue date Oct 4, 2022
- Micron Technology, Inc.
- Gianfranco Ferrante
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface for memory having a cache and multiple independent arrays
- Patent number 11,132,311
- Issue date Sep 28, 2021
- Micron Technology, Inc.
- Dionisio Minopoli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilevel addressing
- Patent number 10,860,474
- Issue date Dec 8, 2020
- Micron Technology, Inc.
- Gianfranco Ferrante
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface for memory having a cache and multiple independent arrays
- Patent number 10,534,731
- Issue date Jan 14, 2020
- Micron Technology, Inc.
- Dionisio Minopoli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for providing file information in a memory syst...
- Patent number 10,175,908
- Issue date Jan 8, 2019
- Micron Technology, Inc.
- Danilo Caraccio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for providing file information in a memory syst...
- Patent number 9,880,772
- Issue date Jan 30, 2018
- Micron Technology, Inc.
- Danilo Caraccio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Erase verification for flash memory
- Patent number 8,014,208
- Issue date Sep 6, 2011
- Micron Technology, Inc.
- Gianfranco Ferrante
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of managing fails in a non-volatile memory device and relati...
- Patent number 7,571,362
- Issue date Aug 4, 2009
- Demetrio Pellicone
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC UPDATES TO LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION TABLE BI...
- Publication number 20240168889
- Publication date May 23, 2024
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC UPDATES TO LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION TABLE BI...
- Publication number 20240061787
- Publication date Feb 22, 2024
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR PAGE LINE FILLER DATA
- Publication number 20230244414
- Publication date Aug 3, 2023
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR PAGE LINE FILLER DATA
- Publication number 20220374163
- Publication date Nov 24, 2022
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-ADAPTIVE WEAR LEVELING METHOD AND ALGORITHM
- Publication number 20210406169
- Publication date Dec 30, 2021
- Micron Technology, Inc.
- Dionisio Minopoli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTILEVEL ADDRESSING
- Publication number 20210089443
- Publication date Mar 25, 2021
- Micron Technology, Inc.
- Gianfranco Ferrante
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE FOR MEMORY HAVING A CACHE AND MULTIPLE INDEPENDENT ARRAYS
- Publication number 20200104268
- Publication date Apr 2, 2020
- Micron Technology, Inc.
- Dionisio Minopoli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE FOR MEMORY HAVING A CACHE AND MULTIPLE INDEPENDENT ARRAYS
- Publication number 20190286586
- Publication date Sep 19, 2019
- Micron Technology, Inc.
- Dionisio Minopoli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTILEVEL ADDRESSING
- Publication number 20190188124
- Publication date Jun 20, 2019
- Micron Technology, Inc.
- Gianfranco Ferrante
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR PROVIDING FILE INFORMATION IN A MEMORY SYST...
- Publication number 20180129442
- Publication date May 10, 2018
- Micron Technology, Inc.
- Danilo Caraccio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR PROVIDING FILE INFORMATION IN A MEMORY SYST...
- Publication number 20170083260
- Publication date Mar 23, 2017
- Micron Technology, Inc.
- Danilo Caraccio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF MANAGING FAILS IN A NON-VOLATILE MEMORY DEVICE AND RELATI...
- Publication number 20070109856
- Publication date May 17, 2007
- STMicroelectronics S.r.I.
- Demetrio Pellicone
- G11 - INFORMATION STORAGE

Gianfranco Ferrante

Person

Patents Grantslast 30 patents

Dynamic updates to logical-to-physical address translation table bi...

Techniques for page line filler data

Techniques for page line filler data

Multilevel addressing

Interface for memory having a cache and multiple independent arrays

Multilevel addressing

Interface for memory having a cache and multiple independent arrays

Systems and methods for providing file information in a memory syst...

Systems and methods for providing file information in a memory syst...

Erase verification for flash memory

Method of managing fails in a non-volatile memory device and relati...

Patents Applicationslast 30 patents

DYNAMIC UPDATES TO LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION TABLE BI...

DYNAMIC UPDATES TO LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION TABLE BI...

TECHNIQUES FOR PAGE LINE FILLER DATA

TECHNIQUES FOR PAGE LINE FILLER DATA

SELF-ADAPTIVE WEAR LEVELING METHOD AND ALGORITHM

MULTILEVEL ADDRESSING

INTERFACE FOR MEMORY HAVING A CACHE AND MULTIPLE INDEPENDENT ARRAYS

INTERFACE FOR MEMORY HAVING A CACHE AND MULTIPLE INDEPENDENT ARRAYS

MULTILEVEL ADDRESSING

SYSTEMS AND METHODS FOR PROVIDING FILE INFORMATION IN A MEMORY SYST...

SYSTEMS AND METHODS FOR PROVIDING FILE INFORMATION IN A MEMORY SYST...

METHOD OF MANAGING FAILS IN A NON-VOLATILE MEMORY DEVICE AND RELATI...