Gigy Baror

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Organization of an integrated cache unit for flexible usage in supp...
- Patent number 6,014,728
- Issue date Jan 11, 2000
- Advanced Micro Devices, Inc.
- Gigy Baror
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Organization of an integrated cache unit for flexible usage in supp...
- Patent number 5,627,992
- Issue date May 6, 1997
- Advanced Micro Devices
- Gigy Baror
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable cache memory as well as system incorporating same and...
- Patent number 5,185,878
- Issue date Feb 9, 1993
- Advanced Micro Device, Inc.
- Gigy Baror
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for caching interlock variables in an integra...
- Patent number 5,136,691
- Issue date Aug 4, 1992
- Advanced Micro Devices, Inc.
- Gigy Baror
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Organization of an integrated cache unit for flexible usage in cach...
- Patent number 5,025,366
- Issue date Jun 18, 1991
- Advanced Micro Devices, Inc.
- Gigy Baror
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streamlined instruction processor
- Patent number 4,926,323
- Issue date May 15, 1990
- Advanced Micro Devices, Inc.
- Gigy Baror
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance processor interface between a single chip processo...
- Patent number 4,851,990
- Issue date Jul 25, 1989
- Advanced Micro Devices, Inc.
- William M. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock scheme for VLSI systems
- Patent number 4,761,567
- Issue date Aug 2, 1988
- Advanced Micro Devices, Inc.
- Donald M. Walters
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Organization of an integrated cache unit for flexible usage in supp...

Organization of an integrated cache unit for flexible usage in supp...

Programmable cache memory as well as system incorporating same and...

Methods and apparatus for caching interlock variables in an integra...

Organization of an integrated cache unit for flexible usage in cach...

Streamlined instruction processor

High performance processor interface between a single chip processo...

Clock scheme for VLSI systems