Gilbert Yoh

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for high speed data parallelization for an N-phas...
- Patent number 8,902,091
- Issue date Dec 2, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Darrin C. Miller
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for generating a constant logical value in an...
- Patent number 7,741,879
- Issue date Jun 22, 2010
- Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Robert Harry Miller, Jr.
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Stable process induced correction bias circuitry for receivers on s...
- Patent number 7,313,372
- Issue date Dec 25, 2007
- Avago Technologies General IP Pte. Ltd.
- Manuel Salcido
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for matching data and clock signal delays to impr...
- Patent number 7,194,053
- Issue date Mar 20, 2007
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Gilbert Yoh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for measuring switching noise in integrated ci...
- Patent number 7,159,160
- Issue date Jan 2, 2007
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Gilbert Yoh
- G01 - MEASURING TESTING
Information Patent Grant
Fixed termination scheme for differential receiver that compensates...
- Patent number 6,766,155
- Issue date Jul 20, 2004
- Agilent Technologies, Inc.
- Manuel Salcido
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Internal bus termination technique for integrated circuits with loc...
- Patent number 6,714,039
- Issue date Mar 30, 2004
- Agilent Technologies, Inc.
- Manuel Salcido
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LOW POWER PARALLELIZATION TO MULTIPLE OUTPUT BUS WIDTHS
- Publication number 20160306765
- Publication date Oct 20, 2016
- Avago Technologies General IP (Singapore) PTE. LTD.
- Darrin C. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method For Adaptive N-Phase Clock Generation For An N-Ph...
- Publication number 20140362962
- Publication date Dec 11, 2014
- Peter J. Meier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Apparatus And Method For Generating A Constant Logical Value In An...
- Publication number 20080204082
- Publication date Aug 28, 2008
- Robert Harry Miller
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Stable process induced correction bias circuitry for receivers on s...
- Publication number 20060025089
- Publication date Feb 2, 2006
- Manuel Salcido
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for measuring switching noise in integrated ci...
- Publication number 20050283698
- Publication date Dec 22, 2005
- Gilbert Yoh
- G01 - MEASURING TESTING
Information Patent Application
Internal bus termination technique for integrated circuits with loc...
- Publication number 20030210070
- Publication date Nov 13, 2003
- Manuel Salcido
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fixed termination scheme for differential receiver that compensates...
- Publication number 20030139164
- Publication date Jul 24, 2003
- Manuel Salcido
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for matching data and clock signal delays to impr...
- Publication number 20030112910
- Publication date Jun 19, 2003
- Gilbert Yoh
- G06 - COMPUTING CALCULATING COUNTING

Gilbert Yoh

Person

Patents Grantslast 30 patents

System and method for high speed data parallelization for an N-phas...

Apparatus and method for generating a constant logical value in an...

Stable process induced correction bias circuitry for receivers on s...

System and method for matching data and clock signal delays to impr...

Method and apparatus for measuring switching noise in integrated ci...

Fixed termination scheme for differential receiver that compensates...

Internal bus termination technique for integrated circuits with loc...

Patents Applicationslast 30 patents

LOW POWER PARALLELIZATION TO MULTIPLE OUTPUT BUS WIDTHS

System and Method For Adaptive N-Phase Clock Generation For An N-Ph...

Apparatus And Method For Generating A Constant Logical Value In An...

Stable process induced correction bias circuitry for receivers on s...

Method and apparatus for measuring switching noise in integrated ci...

Internal bus termination technique for integrated circuits with loc...

Fixed termination scheme for differential receiver that compensates...

System and method for matching data and clock signal delays to impr...