Giovanni De Micheli

Person

Lausanne, CH

People

Patents Grantslast 30 patents

Information Patent Grant
Majority logic synthesis
- Patent number 10,394,988
- Issue date Aug 27, 2019
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Pierre-Emmanuel Julien Gaillardon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boolean logic optimization in majority-inverter graphs
- Patent number 10,380,309
- Issue date Aug 13, 2019
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Luca Gaetano Amarù
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resistive random access memory based multiplexers and field program...
- Patent number 10,348,306
- Issue date Jul 9, 2019
- University of Utah Research Foundation
- Pierre-Emanuel Gaillardon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pattern-based FPGA logic block and clustering algorithm
- Patent number 9,971,862
- Issue date May 15, 2018
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Xifan Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for speeding up boolean satisfiability
- Patent number 9,685,959
- Issue date Jun 20, 2017
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Luca Gaetano Amarú
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resistive switching element and use thereof
- Patent number 9,412,940
- Issue date Aug 9, 2016
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Davide Sacchetto
- G11 - INFORMATION STORAGE
Information Patent Grant
High-performance low-power near-Vt resistive memory-based FPGA
- Patent number 9,276,573
- Issue date Mar 1, 2016
- Ecole Polytechnique Federale de Lausanne
- Pierre-Emmanuel Gaillardon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ambipolar silicon nanowire field effect transistor
- Patent number 9,252,252
- Issue date Feb 2, 2016
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Giovanni De Micheli
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Controllable polarity FET based arithmetic and differential logic
- Patent number 9,130,568
- Issue date Sep 8, 2015
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Luca Gaetano Amaru
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method to design network-on-chip (NOC)-based communication systems
- Patent number 8,042,087
- Issue date Oct 18, 2011
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Srinivasan Murali
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method to manage the load of peripheral elements within a multicore...
- Patent number 7,995,599
- Issue date Aug 9, 2011
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Federico Angiolini
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
RESISTIVE RANDOM ACCESS MEMORY BASED MULTIPLEXERS AND FIELD PROGRAM...
- Publication number 20180262197
- Publication date Sep 13, 2018
- University of Utah Research Foundation
- Pierre-Emanuel Gaillardon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Majority Logic Synthesis
- Publication number 20170177750
- Publication date Jun 22, 2017
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Pierre-Emmanuel Julien Gaillardon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOOLEAN LOGIC OPTIMIZATION IN MAJORITY-INVERTER GRAPHS
- Publication number 20160350469
- Publication date Dec 1, 2016
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Luca Gaetano Amarù
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resistive Switching Element and Use Thereof
- Publication number 20160322101
- Publication date Nov 3, 2016
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Davide Sacchetto
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR SPEEDING UP BOOLEAN SATISFIABILITY
- Publication number 20160077154
- Publication date Mar 17, 2016
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Luca Gaetano AMARÚ
- G01 - MEASURING TESTING
Information Patent Application
PATTERN-BASED FPGA LOGIC BLOCK AND CLUSTERING ALGORITHM
- Publication number 20160063168
- Publication date Mar 3, 2016
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Xifan TANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-PERFORMANCE LOW-POWER NEAR-VT RESISTIVE MEMORY-BASED FPGA
- Publication number 20160028396
- Publication date Jan 28, 2016
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Pierre-Emmanuel Gaillardon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RESISTIVE SWITCHING ELEMENT AND USE THEREOF
- Publication number 20150200363
- Publication date Jul 16, 2015
- Davide Sacchetto
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLABLE POLARITY FET BASED ARITHMETIC AND DIFFERENTIAL LOGIC
- Publication number 20140043060
- Publication date Feb 13, 2014
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Luca Gaetano AMARU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AMBIPOLAR SILICON NANOWIRE FIELD EFFECT TRANSISTOR
- Publication number 20130313524
- Publication date Nov 28, 2013
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Giovanni De Micheli
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD TO MANAGE THE LOAD OF PERIPHERAL ELEMENTS WITHIN A MULTICORE...
- Publication number 20100080124
- Publication date Apr 1, 2010
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Federico Angiolini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO DESIGN NETWORK-ON-CHIP (NOC) - BASED COMMUNICATION SYSTEMS
- Publication number 20090313592
- Publication date Dec 17, 2009
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Srinivasan Murali
- G06 - COMPUTING CALCULATING COUNTING

Giovanni De Micheli

Person

Patents Grantslast 30 patents

Majority logic synthesis

Boolean logic optimization in majority-inverter graphs

Resistive random access memory based multiplexers and field program...

Pattern-based FPGA logic block and clustering algorithm

Method for speeding up boolean satisfiability

Resistive switching element and use thereof

High-performance low-power near-Vt resistive memory-based FPGA

Ambipolar silicon nanowire field effect transistor

Controllable polarity FET based arithmetic and differential logic

Method to design network-on-chip (NOC)-based communication systems

Method to manage the load of peripheral elements within a multicore...

Patents Applicationslast 30 patents

RESISTIVE RANDOM ACCESS MEMORY BASED MULTIPLEXERS AND FIELD PROGRAM...

Majority Logic Synthesis

BOOLEAN LOGIC OPTIMIZATION IN MAJORITY-INVERTER GRAPHS

Resistive Switching Element and Use Thereof

METHOD FOR SPEEDING UP BOOLEAN SATISFIABILITY

PATTERN-BASED FPGA LOGIC BLOCK AND CLUSTERING ALGORITHM

HIGH-PERFORMANCE LOW-POWER NEAR-VT RESISTIVE MEMORY-BASED FPGA

RESISTIVE SWITCHING ELEMENT AND USE THEREOF

CONTROLLABLE POLARITY FET BASED ARITHMETIC AND DIFFERENTIAL LOGIC

AMBIPOLAR SILICON NANOWIRE FIELD EFFECT TRANSISTOR

METHOD TO MANAGE THE LOAD OF PERIPHERAL ELEMENTS WITHIN A MULTICORE...

METHOD TO DESIGN NETWORK-ON-CHIP (NOC) - BASED COMMUNICATION SYSTEMS