Giovanni Naso

Person

Frosinone (FR), IT

People

Patents Grantslast 30 patents

Information Patent Grant
Memory apparatus, systems, and methods
- Patent number 9,646,683
- Issue date May 9, 2017
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold voltage compensation in a memory
- Patent number 9,520,183
- Issue date Dec 13, 2016
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory apparatus, systems, and methods
- Patent number 9,087,594
- Issue date Jul 21, 2015
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold voltage compensation in a multilevel memory
- Patent number 9,030,870
- Issue date May 12, 2015
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Filtered register architecture to generate actuator signals
- Patent number 8,275,926
- Issue date Sep 25, 2012
- Micron Technology, Inc.
- Giovanni Naso
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Filtered register architecture to generate actuator signals
- Patent number 7,934,048
- Issue date Apr 26, 2011
- Micron Technology, Inc.
- Giovanni Naso
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Fuse data acquisition
- Patent number 7,738,310
- Issue date Jun 15, 2010
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Data compression read mode for memory testing
- Patent number 7,657,802
- Issue date Feb 2, 2010
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Output buffer strength trimming
- Patent number 7,635,991
- Issue date Dec 22, 2009
- Micron Technology, Inc.
- Girolamo Gallo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Filtered register architecture to generate actuator signals
- Patent number 7,620,859
- Issue date Nov 17, 2009
- Micron Technology, Inc.
- Giovanni Naso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Background block erase check for flash memories
- Patent number 7,565,587
- Issue date Jul 21, 2009
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple-level data compression read mode for memory testing
- Patent number 7,434,152
- Issue date Oct 7, 2008
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
ROM-based controller monitor in a memory device
- Patent number 7,318,181
- Issue date Jan 8, 2008
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash cell fuse circuit
- Patent number 7,277,311
- Issue date Oct 2, 2007
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Data compression read mode for memory testing
- Patent number 7,254,756
- Issue date Aug 7, 2007
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual bus memory burst architecture
- Patent number 7,164,607
- Issue date Jan 16, 2007
- Micron Technology, Inc.
- Girolamo Gallo
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip protection register unlocking
- Patent number 7,145,799
- Issue date Dec 5, 2006
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Background block erase check for flash memories
- Patent number 7,117,402
- Issue date Oct 3, 2006
- Micron Technology, Inc.
- Maurizio Di Zenzo
- G11 - INFORMATION STORAGE
Information Patent Grant
Output buffer strength trimming
- Patent number 7,064,582
- Issue date Jun 20, 2006
- Micron Technology, Inc.
- Girolamo Gallo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flash cell fuse circuit
- Patent number 7,002,828
- Issue date Feb 21, 2006
- Micron Technology, Inc.
- Giovanni Santin
- G11 - INFORMATION STORAGE
Information Patent Grant
ROM-based controller monitor in a memory device
- Patent number 6,977,852
- Issue date Dec 20, 2005
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Test mode decoder in a flash memory
- Patent number 6,977,410
- Issue date Dec 20, 2005
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip protection register unlocking
- Patent number 6,947,323
- Issue date Sep 20, 2005
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual bus memory burst architecture
- Patent number 6,917,545
- Issue date Jul 12, 2005
- Micron Technology, Inc.
- Girolamo Gallo
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory sector tagging for consecutive sector erase or bank erase
- Patent number 6,909,641
- Issue date Jun 21, 2005
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash cell fuse circuit
- Patent number 6,845,029
- Issue date Jan 18, 2005
- Micron Technology, Inc.
- Giovanni Santin
- G11 - INFORMATION STORAGE
Information Patent Grant
Test mode decoder in a flash memory
- Patent number 6,785,162
- Issue date Aug 31, 2004
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory sector tagging for consecutive sector erase or bank erase
- Patent number 6,717,862
- Issue date Apr 6, 2004
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash cell fuse circuit
- Patent number 6,654,272
- Issue date Nov 25, 2003
- Micron Technology, Inc.
- Giovanni Santin
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash EEPROM array with P-tank insulated from substrate by deep N-tank
- Patent number 5,504,708
- Issue date Apr 2, 1996
- Texas Instruments Incorporated
- Giovanni Santin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MEMORY APPARATUS, SYSTEMS, AND METHODS
- Publication number 20150325309
- Publication date Nov 12, 2015
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
THRESHOLD VOLTAGE COMPENSATION IN A MEMORY
- Publication number 20150243351
- Publication date Aug 27, 2015
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY APPARATUS, SYSTEMS, AND METHODS
- Publication number 20130058164
- Publication date Mar 7, 2013
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
THRESHOLD VOLTAGE COMPENSATION IN A MULTILEVEL MEMORY
- Publication number 20130051141
- Publication date Feb 28, 2013
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
FILTERED REGISTER ARCHITECTURE TO GENERATE ACTUATOR SIGNALS
- Publication number 20110208902
- Publication date Aug 25, 2011
- Giovanni Naso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FILTERED REGISTER ARCHITECTURE TO GENERATE ACTUATOR SIGNALS
- Publication number 20100064188
- Publication date Mar 11, 2010
- Giovanni Naso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSE DATA ACQUISITION
- Publication number 20090067252
- Publication date Mar 12, 2009
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Filtered register architecture to generate actuator signals
- Publication number 20080086604
- Publication date Apr 10, 2008
- Micron Technology, Inc.
- Giovanni Naso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA COMPRESSION READ MODE FOR MEMORY TESTING
- Publication number 20080016419
- Publication date Jan 17, 2008
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Background block erase check for flash memories
- Publication number 20070022332
- Publication date Jan 25, 2007
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Application
Output buffer strength trimming
- Publication number 20060261853
- Publication date Nov 23, 2006
- Girolamo Gallo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multiple-level data compression read more for memory testing
- Publication number 20060044880
- Publication date Mar 2, 2006
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Test mode decoder in a flash memory
- Publication number 20050280072
- Publication date Dec 22, 2005
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
ROM-based controller monitor in a memory device
- Publication number 20050240851
- Publication date Oct 27, 2005
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Chip protection register unlocking
- Publication number 20050237804
- Publication date Oct 27, 2005
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Dual bus memory burst architecture
- Publication number 20050207233
- Publication date Sep 22, 2005
- Micron Technology, Inc.
- Girolamo Gallo
- G11 - INFORMATION STORAGE
Information Patent Application
Test mode decoder in a flash memory
- Publication number 20040246773
- Publication date Dec 9, 2004
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory sector tagging for consecutive sector erase or bank erase
- Publication number 20040240253
- Publication date Dec 2, 2004
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
ROM-based controller monitor in a memory device
- Publication number 20040213060
- Publication date Oct 28, 2004
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Data compression read mode for memory testing
- Publication number 20040153599
- Publication date Aug 5, 2004
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Chip protection register unlocking
- Publication number 20040151026
- Publication date Aug 5, 2004
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Output buffer strength trimming
- Publication number 20040145388
- Publication date Jul 29, 2004
- Micron Technology, Inc.
- Girolamo Gallo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dual bus memory burst architecture
- Publication number 20040071037
- Publication date Apr 15, 2004
- Girolamo Gallo
- G11 - INFORMATION STORAGE
Information Patent Application
Flash cell fuse circuit
- Publication number 20040052121
- Publication date Mar 18, 2004
- Micron Technology, Inc.
- Giovanni Santin
- G11 - INFORMATION STORAGE
Information Patent Application
Flash cell fuse circuit
- Publication number 20040037131
- Publication date Feb 26, 2004
- Micron Technology, Inc.
- Giovanni Santin
- G11 - INFORMATION STORAGE
Information Patent Application
Background block erase check for flash memories
- Publication number 20030101390
- Publication date May 29, 2003
- Maurizio Di Zenzo
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory sector tagging for consecutive sector erase or bank erase
- Publication number 20030063500
- Publication date Apr 3, 2003
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Test mode decoder in a flash memory
- Publication number 20030048673
- Publication date Mar 13, 2003
- Micron Technology, Inc.
- Giovanni Naso
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flash cell fuse circuit
- Publication number 20020122331
- Publication date Sep 5, 2002
- Giovanni Santin
- G11 - INFORMATION STORAGE

Giovanni Naso

Person

Patents Grantslast 30 patents

Memory apparatus, systems, and methods

Threshold voltage compensation in a memory

Memory apparatus, systems, and methods

Threshold voltage compensation in a multilevel memory

Filtered register architecture to generate actuator signals

Filtered register architecture to generate actuator signals

Fuse data acquisition

Data compression read mode for memory testing

Output buffer strength trimming

Filtered register architecture to generate actuator signals

Background block erase check for flash memories

Multiple-level data compression read mode for memory testing

ROM-based controller monitor in a memory device

Flash cell fuse circuit

Data compression read mode for memory testing

Dual bus memory burst architecture

Chip protection register unlocking

Background block erase check for flash memories

Output buffer strength trimming

Flash cell fuse circuit

ROM-based controller monitor in a memory device

Test mode decoder in a flash memory

Chip protection register unlocking

Dual bus memory burst architecture

Flash memory sector tagging for consecutive sector erase or bank erase

Flash cell fuse circuit

Test mode decoder in a flash memory

Flash memory sector tagging for consecutive sector erase or bank erase

Flash cell fuse circuit

Flash EEPROM array with P-tank insulated from substrate by deep N-tank

Patents Applicationslast 30 patents

MEMORY APPARATUS, SYSTEMS, AND METHODS

THRESHOLD VOLTAGE COMPENSATION IN A MEMORY

MEMORY APPARATUS, SYSTEMS, AND METHODS

THRESHOLD VOLTAGE COMPENSATION IN A MULTILEVEL MEMORY

FILTERED REGISTER ARCHITECTURE TO GENERATE ACTUATOR SIGNALS

FILTERED REGISTER ARCHITECTURE TO GENERATE ACTUATOR SIGNALS

FUSE DATA ACQUISITION

Filtered register architecture to generate actuator signals

DATA COMPRESSION READ MODE FOR MEMORY TESTING

Background block erase check for flash memories

Output buffer strength trimming

Multiple-level data compression read more for memory testing

Test mode decoder in a flash memory

ROM-based controller monitor in a memory device

Chip protection register unlocking

Dual bus memory burst architecture

Test mode decoder in a flash memory

Flash memory sector tagging for consecutive sector erase or bank erase

ROM-based controller monitor in a memory device

Data compression read mode for memory testing

Chip protection register unlocking

Output buffer strength trimming

Dual bus memory burst architecture

Flash cell fuse circuit

Flash cell fuse circuit

Background block erase check for flash memories

Flash memory sector tagging for consecutive sector erase or bank erase

Test mode decoder in a flash memory

Flash cell fuse circuit